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Commit 6ce0042a authored by Carter Cooper's avatar Carter Cooper
Browse files

msm: kgsl: Reassign always on register offset when no GMU 



On A6XX, if the GMU is not enabled or not present, use the CP always
on register offset rather than the GMU always on register offset.

Change-Id: Ibb5d096e2b6e5f073d3b28628cb57d010a3d668b
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent 0a21cce4

drivers/gpu/msm/adreno_a6xx.c

+18 −0
Original line number Diff line number Diff line
@@ -103,9 +103,27 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
	adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K;

}



static void _update_always_on_regs(struct adreno_device *adreno_dev)

{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	unsigned int *const regs = gpudev->reg_offsets->offsets;



	regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO] =

		A6XX_CP_ALWAYS_ON_COUNTER_LO;

	regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI] =

		A6XX_CP_ALWAYS_ON_COUNTER_HI;

}



static void a6xx_init(struct adreno_device *adreno_dev)

{

	a6xx_crashdump_init(adreno_dev);



	/*

	 * If the GMU is not enabled, rewrite the offset for the always on

	 * counters to point to the CP always on instead of GMU always on

	 */

	if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev)))

		_update_always_on_regs(adreno_dev);

}



/**