Merge "msm: kgsl: Add GBIF reset sequence for SDM670 GPU" (6c8dbc5c) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/msm/a6xx_reg.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -405,6 +405,7 @@
		#define A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0xF810

		#define A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00010
		#define A6XX_RBBM_GPR0_CNTL 0x00018
		#define A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0001f
		#define A6XX_RBBM_INT_CLEAR_CMD 0x00037
		#define A6XX_RBBM_INT_0_MASK 0x00038
		@@ -809,7 +810,7 @@
		/* GBIF registers */
		#define A6XX_GBIF_HALT 0x3c45
		#define A6XX_GBIF_HALT_ACK 0x3c46
		#define A6XX_GBIF_HALT_MASK 0x1
		#define A6XX_GBIF_HALT_MASK 0x2

		#define A6XX_GBIF_PERF_PWR_CNT_EN 0x3cc0
		#define A6XX_GBIF_PERF_CNT_SEL 0x3cc2

drivers/gpu/msm/adreno.h

+23 −7

Original line number	Diff line number	Diff line
		@@ -226,6 +226,10 @@ enum adreno_gpurev {
		#define ADRENO_HWCG_CTRL 3
		#define ADRENO_THROTTLING_CTRL 4

		/* VBIF, GBIF halt request and ack mask */
		#define GBIF_HALT_REQUEST 0x1E0
		#define VBIF_RESET_ACK_MASK 0x00f0
		#define VBIF_RESET_ACK_TIMEOUT 100

		/* number of throttle counters for DCVS adjustment */
		#define ADRENO_GPMU_THROTTLE_COUNTERS 4
		@@ -683,6 +687,8 @@ enum adreno_regs {
		ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE,
		ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI,
		ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE,
		ADRENO_REG_RBBM_GPR0_CNTL,
		ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS,
		ADRENO_REG_VBIF_XIN_HALT_CTRL0,
		ADRENO_REG_VBIF_XIN_HALT_CTRL1,
		ADRENO_REG_VBIF_VERSION,
		@@ -1889,17 +1895,15 @@ static inline bool adreno_has_gbif(struct adreno_device *adreno_dev)
		* @ack_reg: register offset to wait for acknowledge
		*/
		static inline int adreno_wait_for_vbif_halt_ack(struct kgsl_device *device,
		int ack_reg)
		int ack_reg, unsigned int mask)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		unsigned long wait_for_vbif;
		unsigned int mask = gpudev->vbif_xin_halt_ctrl0_mask;
		unsigned int val;
		int ret = 0;

		/* wait for the transactions to clear */
		wait_for_vbif = jiffies + msecs_to_jiffies(100);
		wait_for_vbif = jiffies + msecs_to_jiffies(VBIF_RESET_ACK_TIMEOUT);
		while (1) {
		adreno_readreg(adreno_dev, ack_reg,
		&val);
		@@ -1929,15 +1933,27 @@ static inline int adreno_vbif_clear_pending_transactions(
		int ret = 0;

		if (adreno_has_gbif(adreno_dev)) {
		/*
		* Halt GBIF GX first and then CX part.
		* Need to release CX Halt explicitly in case of SW_RESET.
		* GX Halt release will be taken care by SW_RESET internally.
		*/
		adreno_writereg(adreno_dev, ADRENO_REG_RBBM_GPR0_CNTL,
		GBIF_HALT_REQUEST);
		ret = adreno_wait_for_vbif_halt_ack(device,
		ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS,
		VBIF_RESET_ACK_MASK);
		if (ret)
		return ret;

		adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, mask);
		ret = adreno_wait_for_vbif_halt_ack(device,
		ADRENO_REG_GBIF_HALT_ACK);
		adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, 0);
		ADRENO_REG_GBIF_HALT_ACK, mask);
		} else {
		adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0,
		mask);
		ret = adreno_wait_for_vbif_halt_ack(device,
		ADRENO_REG_VBIF_XIN_HALT_CTRL1);
		ADRENO_REG_VBIF_XIN_HALT_CTRL1, mask);
		adreno_writereg(adreno_dev, ADRENO_REG_VBIF_XIN_HALT_CTRL0, 0);
		}
		return ret;

drivers/gpu/msm/adreno_a6xx.c

+19 −4

Original line number	Diff line number	Diff line
		@@ -2049,8 +2049,7 @@ static int a6xx_microcode_read(struct adreno_device *adreno_dev)
		return _load_gmu_firmware(device);
		}

		#define VBIF_RESET_ACK_TIMEOUT 100
		#define VBIF_RESET_ACK_MASK 0x00f0
		#define GBIF_CX_HALT_MASK BIT(1)

		static int a6xx_soft_reset(struct adreno_device *adreno_dev)
		{
		@@ -2091,6 +2090,13 @@ static int a6xx_soft_reset(struct adreno_device *adreno_dev)
		if (!vbif_acked)
		return -ETIMEDOUT;

		/*
		* GBIF GX halt will be released automatically by sw_reset.
		* Release GBIF CX halt after sw_reset
		*/
		if (adreno_has_gbif(adreno_dev))
		kgsl_regrmw(device, A6XX_GBIF_HALT, GBIF_CX_HALT_MASK, 0);

		a6xx_sptprac_enable(adreno_dev);

		return 0;
		@@ -2307,8 +2313,14 @@ static int a6xx_reset(struct kgsl_device *device, int fault)
		udelay(100);
		}

		if (acked)
		if (acked) {
		/* Make sure VBIF/GBIF is cleared before resetting */
		ret = adreno_vbif_clear_pending_transactions(device);

		if (ret == 0)
		ret = adreno_soft_reset(device);
		}

		if (ret)
		KGSL_DEV_ERR_ONCE(device, "Device soft reset failed\n");
		}
		@@ -3645,6 +3657,9 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
		A6XX_VBIF_XIN_HALT_CTRL0),
		ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL1,
		A6XX_VBIF_XIN_HALT_CTRL1),
		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GPR0_CNTL, A6XX_RBBM_GPR0_CNTL),
		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS,
		A6XX_RBBM_VBIF_GX_RESET_STATUS),
		ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT),
		ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT_ACK, A6XX_GBIF_HALT_ACK),
		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO,