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Commit 6c846e3a authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: Add clock driver support for SDM845 v2 



Pull in the changes to the frequency plan for the peripheral,
camera, display and video clocks between the two versions
of SDM845.

Change-Id: I62bdf9774b2b66da47033ebe38d857e50e85894a
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 7529b53b

Documentation/devicetree/bindings/clock/qcom,camcc.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies Camera Clock & Reset Controller Binding 
----------------------------------------------------



Required properties :

- compatible : shall contain "qcom,cam_cc-sdm845"

- compatible : shall contain "qcom,cam_cc-sdm845" or "qcom,cam_cc-sdm845-v2"

- reg : shall contain base register location and length

- reg-names: names of registers listed in the same order as in

	     the reg property.

Documentation/devicetree/bindings/clock/qcom,dispcc.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding 
----------------------------------------------------



Required properties :

- compatible : shall contain "qcom,dispcc-sdm845".

- compatible : shall contain "qcom,dispcc-sdm845" or "qcom,dispcc-sdm845-v2".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ Required properties : 
			"qcom,gcc-msm8996"

			"qcom,gcc-mdm9615"

			"qcom,gcc-sdm845"

			"qcom,gcc-sdm845-v2"

			"qcom,debugcc-sdm845"



- reg : shall contain base register location and length

Documentation/devicetree/bindings/clock/qcom,videocc.txt

+5 −4
Original line number Diff line number Diff line
@@ -2,12 +2,13 @@ Qualcomm Technologies Video Clock & Reset Controller Binding 
----------------------------------------------------



Required properties :

- compatible : shall contain "qcom,video_cc-sdm845"

- reg : shall contain base register location and length

- compatible : shall contain "qcom,video_cc-sdm845" or

	       "qcom,video_cc-sdm845-v2".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

- #clock-cells : shall contain 1

- #reset-cells : shall contain 1

- #clock-cells : shall contain 1.

- #reset-cells : shall contain 1.



Optional properties :

- vdd_<rail>-supply: The logic rail supply.

drivers/clk/qcom/camcc-sdm845.c

+136 −0
Original line number Diff line number Diff line
@@ -345,6 +345,12 @@ static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src_sdm845_v2[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),

	{ }

};



static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {

	.cmd_rcgr = 0x9060,

	.mnd_width = 0,
@@ -429,6 +435,25 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 
	},

};



static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {

	.cmd_rcgr = 0x5070,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = NULL,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_csi3phytimer_clk_src",

		.parent_names = cam_cc_parent_names_0,

		.num_parents = 6,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP3(

			MIN, 19200000,

			LOWER, 240000000,

			LOW, 269333333),

	},

};



static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
@@ -469,6 +494,15 @@ static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src_sdm845_v2[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),

	F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),

	F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),

	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),

	{ }

};



static struct clk_rcg2 cam_cc_fd_core_clk_src = {

	.cmd_rcgr = 0xb0b0,

	.mnd_width = 0,
@@ -500,6 +534,15 @@ static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_cam_cc_icp_clk_src_sdm845_v2[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(384000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),

	F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),

	F(538666667, P_CAM_CC_PLL1_OUT_EVEN, 1.5, 0, 0),

	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),

	{ }

};



static struct clk_rcg2 cam_cc_icp_clk_src = {

	.cmd_rcgr = 0xb088,

	.mnd_width = 0,
@@ -755,6 +798,16 @@ static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { 
	{ }

};



static const struct freq_tbl ftbl_cam_cc_lrme_clk_src_sdm845_v2[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),

	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),

	F(269333333, P_CAM_CC_PLL1_OUT_EVEN, 3, 0, 0),

	F(320000000, P_CAM_CC_PLL2_OUT_EVEN, 1.5, 0, 0),

	F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),

	{ }

};



static struct clk_rcg2 cam_cc_lrme_clk_src = {

	.cmd_rcgr = 0xb0f8,

	.mnd_width = 0,
@@ -1073,6 +1126,24 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { 
	},

};



static struct clk_branch cam_cc_csi3phytimer_clk = {

	.halt_reg = 0x5088,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x5088,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csi3phytimer_clk",

			.parent_names = (const char *[]){

				"cam_cc_csi3phytimer_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch cam_cc_csiphy0_clk = {

	.halt_reg = 0x5020,

	.halt_check = BRANCH_HALT,
@@ -1130,6 +1201,25 @@ static struct clk_branch cam_cc_csiphy2_clk = { 
	},

};



static struct clk_branch cam_cc_csiphy3_clk = {

	.halt_reg = 0x508c,

	.halt_check = BRANCH_HALT,

	.aggr_sibling_rates = true,

	.clkr = {

		.enable_reg = 0x508c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_csiphy3_clk",

			.parent_names = (const char *[]){

				"cam_cc_cphy_rx_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch cam_cc_fd_core_clk = {

	.halt_reg = 0xb0c8,

	.halt_check = BRANCH_HALT,
@@ -1763,9 +1853,12 @@ static struct clk_regmap *cam_cc_sdm845_clocks[] = { 
	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,

	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,

	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,

	[CAM_CC_CSI3PHYTIMER_CLK] = NULL,

	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL,

	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,

	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,

	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,

	[CAM_CC_CSIPHY3_CLK] = NULL,

	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,

	[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,

	[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
@@ -1874,10 +1967,49 @@ static const struct qcom_cc_desc cam_cc_sdm845_desc = { 


static const struct of_device_id cam_cc_sdm845_match_table[] = {

	{ .compatible = "qcom,cam_cc-sdm845" },

	{ .compatible = "qcom,cam_cc-sdm845-v2" },

	{ }

};

MODULE_DEVICE_TABLE(of, cam_cc_sdm845_match_table);



static void cam_cc_sdm845_fixup_sdm845v2(void)

{

	cam_cc_sdm845_clocks[CAM_CC_CSI3PHYTIMER_CLK] =

		&cam_cc_csi3phytimer_clk.clkr;

	cam_cc_sdm845_clocks[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr;

	cam_cc_sdm845_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] =

		&cam_cc_csi3phytimer_clk_src.clkr;

	cam_cc_cphy_rx_clk_src.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src_sdm845_v2;

	cam_cc_cphy_rx_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 384000000;

	cam_cc_fd_core_clk_src.freq_tbl = ftbl_cam_cc_fd_core_clk_src_sdm845_v2;

	cam_cc_fd_core_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 384000000;

	cam_cc_icp_clk_src.freq_tbl = ftbl_cam_cc_icp_clk_src_sdm845_v2;

	cam_cc_icp_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 384000000;

	cam_cc_icp_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW_L1] = 600000000;

	cam_cc_ipe_0_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = 600000000;

	cam_cc_ipe_1_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = 600000000;

	cam_cc_lrme_clk_src.freq_tbl = ftbl_cam_cc_lrme_clk_src_sdm845_v2;

	cam_cc_lrme_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW] = 269333333;

	cam_cc_lrme_clk_src.clkr.hw.init->rate_max[VDD_CX_LOW_L1] = 320000000;

	cam_cc_lrme_clk_src.clkr.hw.init->rate_max[VDD_CX_NOMINAL] = 400000000;

	cam_cc_slow_ahb_clk_src.clkr.hw.init->rate_max[VDD_CX_LOWER] = 80000000;

}



static int cam_cc_sdm845_fixup(struct platform_device *pdev)

{

	const char *compat = NULL;

	int compatlen = 0;



	compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen);

	if (!compat || (compatlen <= 0))

		return -EINVAL;



	if (!strcmp(compat, "qcom,cam_cc-sdm845-v2"))

		cam_cc_sdm845_fixup_sdm845v2();



	return 0;

}



static int cam_cc_sdm845_probe(struct platform_device *pdev)

{

	struct regmap *regmap;
@@ -1905,6 +2037,10 @@ static int cam_cc_sdm845_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_mx.regulator[0]);

	}



	ret = cam_cc_sdm845_fixup(pdev);

	if (ret)

		return ret;



	clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);

	clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);

	clk_fabia_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);