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Commit 6be7f534 authored by Takashi Iwai's avatar Takashi Iwai
Browse files

Merge tag 'asoc-3.8p1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next 

ASoC: More updates for v3.8

Nothing terribly exciting here, just small localised changes.

As well as fixes there are a couple of Cirrus changes and one devm_
change which were in prior to the merge window but got missed from the
original pull to Takashi.
parents df68f106 8246b5b0

Makefile

+5 −3
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 7

SUBLEVEL = 0

EXTRAVERSION = -rc7

EXTRAVERSION =

NAME = Terrified Chipmunk



# *DOCUMENTATION*
@@ -1321,10 +1321,12 @@ kernelversion: 


# Clear a bunch of variables before executing the submake

tools/: FORCE

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/

	$(Q)mkdir -p $(objtree)/tools

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= O=$(objtree) subdir=tools -C $(src)/tools/



tools/%: FORCE

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/ $*

	$(Q)mkdir -p $(objtree)/tools

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= O=$(objtree) subdir=tools -C $(src)/tools/ $*



# Single targets

# ---------------------------------------------------------------------------

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -547,6 +547,7 @@ config ARCH_KIRKWOOD 
	select CPU_FEROCEON

	select GENERIC_CLOCKEVENTS

	select PCI

	select PCI_QUIRKS

	select PLAT_ORION_LEGACY

	help

	  Support for the following Marvell Kirkwood series SoCs:

arch/arm/boot/compressed/head.S

+13 −1
Original line number Diff line number Diff line
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
		mov	pc, lr

ENDPROC(__setup_mmu)



@ Enable unaligned access on v6, to allow better code generation

@ for the decompressor C code:

__armv6_mmu_cache_on:

		mrc	p15, 0, r0, c1, c0, 0	@ read SCTLR

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

		mcr	p15, 0, r0, c1, c0, 0	@ write SCTLR

		b	__armv4_mmu_cache_on



__arm926ejs_mmu_cache_on:

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

		mov	r0, #4			@ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on: 
		bic	r0, r0, #1 << 28	@ clear SCTLR.TRE

		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement

		orr	r0, r0, #0x003c		@ write buffer

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

						@ (needed for ARM1176)

#ifdef CONFIG_MMU

#ifdef CONFIG_CPU_ENDIAN_BE8

		orr	r0, r0, #1 << 25	@ big-endian page tables
@@ -914,7 +926,7 @@ proc_types: 


		.word	0x0007b000		@ ARMv6

		.word	0x000ff000

		W(b)	__armv4_mmu_cache_on

		W(b)	__armv6_mmu_cache_on

		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush

arch/arm/boot/dts/at91sam9260.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -217,7 +217,7 @@ 
				compatible = "atmel,at91rm9200-ssc";

				reg = <0xfffbc000 0x4000>;

				interrupts = <14 4 5>;

				status = "disable";

				status = "disabled";

			};



			adc0: adc@fffe0000 {

arch/arm/boot/dts/at91sam9263.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -179,14 +179,14 @@ 
				compatible = "atmel,at91rm9200-ssc";

				reg = <0xfff98000 0x4000>;

				interrupts = <16 4 5>;

				status = "disable";

				status = "disabled";

			};



			ssc1: ssc@fff9c000 {

				compatible = "atmel,at91rm9200-ssc";

				reg = <0xfff9c000 0x4000>;

				interrupts = <17 4 5>;

				status = "disable";

				status = "disabled";

			};



			macb0: ethernet@fffbc000 {