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Commit 6bc57c17 authored by Pavan Kumar Chilamkurthi's avatar Pavan Kumar Chilamkurthi
Browse files

ARM: dts: msm: Add OPP table entries for CAM CC clocks on sdm845 



Tag camera nodes and add opp-handle entries for camera src clocks
in clock_camcc node. These entries trigger clock driver to
populate OPP table for given camera node 'dev' with corresponding
src clk frequencies.

CRs-Fixed: 2019539
Change-Id: Ie1228a9fc383eba06950de8b4901768a2d3f8d5b
Signed-off-by: default avatarPavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
parent 823e0419

arch/arm64/boot/dts/qcom/sdm845-camera-sensor-cdp.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 
	};

};



&cci {

&cam_cci {

	actuator_rear: qcom,actuator@0 {

		cell-index = <0>;

		reg = <0x0>;

arch/arm64/boot/dts/qcom/sdm845-camera-sensor-mtp.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ 
	};

};



&cci {

&cam_cci {

	actuator_rear: qcom,actuator@0 {

		cell-index = <0>;

		reg = <0x0>;

arch/arm64/boot/dts/qcom/sdm845-camera.dtsi

+14 −14
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
		status = "ok";

	};



	qcom,csiphy@ac65000 {

	cam_csiphy0: qcom,csiphy@ac65000 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v1.0", "qcom,csiphy";

		reg = <0x0ac65000 0x1000>;
@@ -53,7 +53,7 @@ 
		status = "ok";

	};



	qcom,csiphy@ac66000{

	cam_csiphy1: qcom,csiphy@ac66000{

		cell-index = <1>;

		compatible = "qcom,csiphy-v1.0", "qcom,csiphy";

		reg = <0xac66000 0x1000>;
@@ -90,7 +90,7 @@ 
		status = "ok";

	};



	qcom,csiphy@ac67000 {

	cam_csiphy2: qcom,csiphy@ac67000 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.0", "qcom,csiphy";

		reg = <0xac67000 0x1000>;
@@ -126,7 +126,7 @@ 
		status = "ok";

	};



	cci: qcom,cci@ac4a000 {

	cam_cci: qcom,cci@ac4a000 {

		cell-index = <0>;

		compatible = "qcom,cci";

		reg = <0xac4a000 0x4000>;
@@ -503,7 +503,7 @@ 
		status = "ok";

	};



	qcom,csid0@acb3000 {

	cam_csid0: qcom,csid0@acb3000 {

		cell-index = <0>;

		compatible = "qcom,csid170";

		reg-names = "csid";
@@ -545,7 +545,7 @@ 
		status = "ok";

	};



	qcom,vfe0@acaf000 {

	cam_vfe0: qcom,vfe0@acaf000 {

		cell-index = <0>;

		compatible = "qcom,vfe170";

		reg-names = "ife";
@@ -582,7 +582,7 @@ 
		status = "ok";

	};



	qcom,csid1@acba000 {

	cam_csid1: qcom,csid1@acba000 {

		cell-index = <1>;

		compatible = "qcom,csid170";

		reg-names = "csid";
@@ -624,7 +624,7 @@ 
		status = "ok";

	};



	qcom,vfe1@acb6000 {

	cam_vfe1: qcom,vfe1@acb6000 {

		cell-index = <1>;

		compatible = "qcom,vfe170";

		reg-names = "ife";
@@ -661,7 +661,7 @@ 
		status = "ok";

	};



	qcom,csid-lite@acc8000 {

	cam_csid_lite: qcom,csid-lite@acc8000 {

		cell-index = <2>;

		compatible = "qcom,csid-lite170";

		reg-names = "csid-lite";
@@ -700,7 +700,7 @@ 
		status = "ok";

	};



	qcom,vfe-lite@acc4000 {

	cam_vfe_lite: qcom,vfe-lite@acc4000 {

		cell-index = <2>;

		compatible = "qcom,vfe-lite170";

		reg-names = "ife-lite";
@@ -743,7 +743,7 @@ 
		status = "ok";

	};



	qcom,a5@ac00000 {

	cam_a5: qcom,a5@ac00000 {

		cell-index = <0>;

		compatible = "qcom,cam_a5";

		reg = <0xac00000 0x6000>,
@@ -783,7 +783,7 @@ 
		status = "ok";

	};



	qcom,ipe0 {

	cam_ipe0: qcom,ipe0 {

		cell-index = <0>;

		compatible = "qcom,cam_ipe";

		regulator-names = "ipe0-vdd";
@@ -803,7 +803,7 @@ 
		status = "ok";

	};



	qcom,ipe1 {

	cam_ipe1: qcom,ipe1 {

		cell-index = <1>;

		compatible = "qcom,cam_ipe";

		regulator-names = "ipe1-vdd";
@@ -823,7 +823,7 @@ 
		status = "ok";

	};



	qcom,bps {

	cam_bps: qcom,bps {

		cell-index = <0>;

		compatible = "qcom,cam_bps";

		regulator-names = "bps-vdd";

arch/arm64/boot/dts/qcom/sdm845.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -1012,6 +1012,20 @@ 
		reg-names = "cc_base";

		vdd_cx-supply = <&pm8998_s9_level>;

		vdd_mx-supply = <&pm8998_s6_level>;

		qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>;

		qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>;

		qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>;

		qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>;

		qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>;

		qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>;

		qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>;

		qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>;

		qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>;

		qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>;

		qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>;

		qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>;

		qcom,cam_cc_ipe_1_clk_src-opp-handle = <&cam_ipe1>;

		qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};