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Commit 6b4fb671 authored by Dong Aisheng's avatar Dong Aisheng Committed by Chris Ball
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mmc: sdhci-esdhc-imx: fix reading cap_1 register value for mx6sl 



When reading CAP_1 register for mx6sl, ignore bit[0-15] as it stores
CAP_2 register value which is new introduced in mx6sl.

Without this fix, the max clock for mx6sl may not be correct since
it's wrongly calculated by reading CAP_1 register.

Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent 6e9fd28e

drivers/mmc/host/sdhci-esdhc-imx.c

+4 −0
Original line number Diff line number Diff line
@@ -226,6 +226,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 
	}



	if (unlikely(reg == SDHCI_CAPABILITIES)) {

		/* ignore bit[0-15] as it stores cap_1 register val for mx6sl */

		if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)

			val &= 0xffff0000;



		/* In FSL esdhc IC module, only bit20 is used to indicate the

		 * ADMA2 capability of esdhc, but this bit is messed up on

		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they