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Commit 6b1814cd authored by Maxime Coquelin stm32's avatar Maxime Coquelin stm32 Committed by Russell King
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ARM: 8340/1: ARMv7-M: Enlarge vector table up to 256 entries 



From Cortex-M reference manuals, the nvic supports up to 240 interrupts.
So the number of entries in vectors table is up to 256.

This patch adds a new config flag to specify the number of external interrupts.
Some ifdeferies are added in order to respect the natural alignment without
wasting too much space on smaller systems.

Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: default avatarStefan Agner <stefan@agner.ch>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b787f68c

arch/arm/kernel/entry-v7m.S

+9 −4
Original line number Diff line number Diff line
@@ -117,9 +117,14 @@ ENTRY(__switch_to) 
ENDPROC(__switch_to)



	.data

	.align	8

#if CONFIG_CPU_V7M_NUM_IRQ <= 112

	.align	9

#else

	.align	10

#endif



/*

 * Vector table (64 words => 256 bytes natural alignment)

 * Vector table (Natural alignment need to be ensured)

 */

ENTRY(vector_table)

	.long	0			@ 0 - Reset stack pointer
@@ -138,6 +143,6 @@ ENTRY(vector_table) 
	.long	__invalid_entry		@ 13 - Reserved

	.long	__pendsv_entry		@ 14 - PendSV

	.long	__invalid_entry		@ 15 - SysTick

	.rept	64 - 16

	.long	__irq_entry		@ 16..64 - External Interrupts

	.rept	CONFIG_CPU_V7M_NUM_IRQ

	.long	__irq_entry		@ External Interrupts

	.endr

arch/arm/mm/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -604,6 +604,21 @@ config CPU_USE_DOMAINS 
	  This option enables or disables the use of domain switching

	  via the set_fs() function.



config CPU_V7M_NUM_IRQ

	int "Number of external interrupts connected to the NVIC"

	depends on CPU_V7M

	default 90 if ARCH_STM32

	default 38 if ARCH_EFM32

	default 240

	help

	  This option indicates the number of interrupts connected to the NVIC.

	  The value can be larger than the real number of interrupts supported

	  by the system, but must not be lower.

	  The default value is 240, corresponding to the maximum number of

	  interrupts supported by the NVIC on Cortex-M family.



	  If unsure, keep default value.



#

# CPU supports 36-bit I/O

#