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Commit 6afc0c26 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'linus' into perf/core, to pick up fixes before applying new changes 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 968d712a 097f70b3

Documentation/devicetree/bindings/arm/gic-v3.txt

+5 −0
Original line number Diff line number Diff line
@@ -57,6 +57,8 @@ used to route Message Signalled Interrupts (MSI) to the CPUs. 
These nodes must have the following properties:

- compatible : Should at least contain  "arm,gic-v3-its".

- msi-controller : Boolean property. Identifies the node as an MSI controller

- #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device

  which will generate the MSI.

- reg: Specifies the base physical address and size of the ITS

  registers.
@@ -83,6 +85,7 @@ Examples: 
		gic-its@2c200000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0x2c200000 0 0x200000>;

		};

	};
@@ -107,12 +110,14 @@ Examples: 
		gic-its@2c200000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0x2c200000 0 0x200000>;

		};



		gic-its@2c400000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

			#msi-cells = <1>;

			reg = <0x0 0x2c400000 0 0x200000>;

		};

	};

Documentation/devicetree/bindings/arm/idle-states.txt

+1 −1
Original line number Diff line number Diff line
@@ -497,7 +497,7 @@ cpus { 
	};



	idle-states {

		entry-method = "arm,psci";

		entry-method = "psci";



		CPU_RETENTION_0_0: cpu-retention-0-0 {

			compatible = "arm,idle-state";

Documentation/devicetree/bindings/gpio/gpio.txt

+3 −1
Original line number Diff line number Diff line
@@ -16,7 +16,9 @@ properties, each containing a 'gpio-list': 
GPIO properties should be named "[<name>-]gpios", with <name> being the purpose

of this GPIO for the device. While a non-existent <name> is considered valid

for compatibility reasons (resolving to the "gpios" property), it is not allowed

for new bindings.

for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old

bindings use it, but are only supported for compatibility reasons and should not

be used for newer bindings since it has been deprecated.



GPIO properties can contain one or more GPIO phandles, but only in exceptional

cases should they contain more than one. If your device uses several GPIOs with

Documentation/devicetree/bindings/iio/accel/bma180.txt

+6 −2
Original line number Diff line number Diff line 
* Bosch BMA180 triaxial acceleration sensor

* Bosch BMA180 / BMA250 triaxial acceleration sensor



http://omapworld.com/BMA180_111_1002839.pdf

http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf



Required properties:



  - compatible : should be "bosch,bma180"

  - compatible : should be "bosch,bma180" or "bosch,bma250"

  - reg : the I2C address of the sensor



Optional properties:
@@ -13,6 +14,9 @@ Optional properties: 


  - interrupts : interrupt mapping for GPIO IRQ, it should by configured with

		flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING

		For the bma250 the first interrupt listed must be the one

		connected to the INT1 pin, the second (optional) interrupt

		listed must be the one connected to the INT2 pin.



Example:

Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt

+18 −2
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority 
interrupt.



Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"

  as fallback

- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or

  "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"

- reg: Base address and size of the controllers memory area

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.
@@ -13,6 +13,9 @@ Required Properties: 
- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 1



Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,

use ar7240 for all other SoCs.



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.
@@ -28,3 +31,16 @@ Example: 
		interrupt-controller;

		#interrupt-cells = <1>;

	};



Another example:



	interrupt-controller@18060010 {

		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";

		reg = <0x18060010 0x4>;



		interrupt-parent = <&cpuintc>;

		interrupts = <6>;



		interrupt-controller;

		#interrupt-cells = <1>;

	};