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Commit 6aaf5a49 authored by Stefan Agner's avatar Stefan Agner
Browse files

drm/fsl-dcu: store layer registers in soc_data 



Store the number of registers per layer in soc_data. This is
more consistent with how the rest of SoC specific data are
handled.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
parent 917f4253

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c

+2 −6
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) 
{

	struct drm_plane *primary;

	struct drm_crtc *crtc = &fsl_dev->crtc;

	unsigned int i, j, reg_num;

	unsigned int i, j;

	int ret;



	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
@@ -154,12 +154,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) 


	drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);



	if (!strcmp(fsl_dev->soc->name, "ls1021a"))

		reg_num = LS1021A_LAYER_REG_NUM;

	else

		reg_num = VF610_LAYER_REG_NUM;

	for (i = 0; i < fsl_dev->soc->total_layer; i++) {

		for (j = 1; j <= reg_num; j++)

		for (j = 1; j <= fsl_dev->soc->layer_regs; j++)

			regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);

	}

	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c

+2 −0
Original line number Diff line number Diff line
@@ -274,12 +274,14 @@ static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = { 
	.name = "ls1021a",

	.total_layer = 16,

	.max_layer = 4,

	.layer_regs = LS1021A_LAYER_REG_NUM,

};



static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {

	.name = "vf610",

	.total_layer = 64,

	.max_layer = 6,

	.layer_regs = VF610_LAYER_REG_NUM,

};



static const struct of_device_id fsl_dcu_of_match[] = {

drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -175,6 +175,7 @@ struct fsl_dcu_soc_data { 
	unsigned int total_layer;

	/*max layer number DCU supported*/

	unsigned int max_layer;

	unsigned int layer_regs;

};



struct fsl_dcu_drm_device {