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Commit 6a908a8a authored by Jeyaprakash Soundrapandian's avatar Jeyaprakash Soundrapandian Committed by Gerrit - the friendly Code Review server
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Merge "DOWNSTREAM: Fastfoward camx Topic branch to AU200" into dev/msm-4.9-camx

parents e87f1ee0 76fd21f6

Documentation/ABI/testing/sysfs-bus-usb-lvstest

+13 −0
Original line number Original line Diff line number Diff line
@@ -45,3 +45,16 @@ Contact: Pratyush Anand <pratyush.anand@gmail.com> 
Description:

Description:

		Write to this node to issue "U3 exit" for Link Layer

		Write to this node to issue "U3 exit" for Link Layer

		Validation device. It is needed for TD.7.36.

		Validation device. It is needed for TD.7.36.



What:		/sys/bus/usb/devices/.../enable_compliance

Date:		July 2017

Description:

		Write to this node to set the port to compliance mode to test

		with Link Layer Validation device. It is needed for TD.7.34.



What:		/sys/bus/usb/devices/.../warm_reset

Date:		July 2017

Description:

		Write to this node to issue "Warm Reset" for Link Layer Validation

		device. It may be needed to properly reset an xHCI 1.1 host port if

		compliance mode needed to be explicitly enabled.

Documentation/devicetree/bindings/arm/msm/qcom,osm.txt

+33 −2
Original line number Original line Diff line number Diff line
@@ -233,8 +233,6 @@ Properties: 
		    configuration registers for the Performance cluster.

		    configuration registers for the Performance cluster.

		    The array must contain exactly three elements.

		    The array must contain exactly three elements.





		    corresponding CPRh device.



- qcom,perfcl-apcs-mem-acc-threshold-voltage

- qcom,perfcl-apcs-mem-acc-threshold-voltage

	Usage:      optional

	Usage:      optional

	Value type: <u32>

	Value type: <u32>
@@ -245,6 +243,27 @@ Properties: 
		    the MEM ACC threshold voltage specified for the

		    the MEM ACC threshold voltage specified for the

		    corresponding CPRh device.

		    corresponding CPRh device.





- qcom,l3-memacc-level-vc-binX

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: Array which defines the NOM and TURBO VCs for the L3 clock

		    on that BIN part.

		    The array must contain exactly two elements.



- qcom,pwrcl-memacc-level-vc-binX

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: Array which defines the NOM and TURBO VCs for the Power

		    cluster clock on that BIN part.

		    The array must contain exactly two elements.



- qcom,perfcl-memacc-level-vc-binX

	Usage:      required

	Value type: <prop-encoded-array>

	Definition: Array which defines the NOM and TURBO VCs for the

		    Performance cluster clock on that BIN part.

		    The array must contain exactly two elements.



- qcom,apcs-cbc-addr

- qcom,apcs-cbc-addr

	Usage:      required

	Usage:      required

	Value type: <prop-encoded-array>

	Value type: <prop-encoded-array>
@@ -483,6 +502,18 @@ Example: 
			<  1881600000 0x404c1462 0x00004e4e 0x2 21 >,

			<  1881600000 0x404c1462 0x00004e4e 0x2 21 >,

			<  1958400000 0x404c1566 0x00005252 0x3 22 >;

			<  1958400000 0x404c1566 0x00005252 0x3 22 >;





		qcom,l3-memacc-level-vc-bin0 = <7 63>;

		qcom,l3-memacc-level-vc-bin1 = <7 9>;

		qcom,l3-memacc-level-vc-bin2 = <7 9>;



		qcom,pwrcl-memacc-level-vc-bin0 = <12 63>;

		qcom,pwrcl-memacc-level-vc-bin1 = <12 17>;

		qcom,pwrcl-memacc-level-vc-bin2 = <12 17>;



		qcom,perfcl-memacc-level-vc-bin0 = <12 18>;

		qcom,perfcl-memacc-level-vc-bin1 = <12 18>;

		qcom,perfcl-memacc-level-vc-bin2 = <12 18>;



		qcom,up-timer =

		qcom,up-timer =

			<1000 1000 1000>;

			<1000 1000 1000>;

		qcom,down-timer =

		qcom,down-timer =

Documentation/devicetree/bindings/arm/msm/qsee_ipc_irq_bridge.txt

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+30 −0
Original line number Original line Diff line number Diff line 
Qualcomm Technologies, Inc. Secure Execution Environment IPC Interrupt Bridge



[Root level node]

Required properties:

-compatible : should be "qcom,qsee-ipc-irq-bridge";



[Second level nodes]

qcom,qsee-ipc-irq-subsystem

Required properties:

-qcom,dev-name: the bridge device name

-interrupt: IPC interrupt line from remote subsystem to QSEE

-label : The name of this subsystem.



Required properties if interrupt type is IRQ_TYPE_LEVEL_HIGH[4]:

-qcom,rx-irq-clr : the register to clear the level triggered rx interrupt

-qcom,rx-irq-clr-mask : the bitmask to clear the rx interrupt



Example:



	qcom,qsee_ipc_irq_bridge {

		compatible = "qcom,qsee-ipc-irq-bridge";



		qcom,qsee-ipc-irq-spss {

			qcom,rx-irq-clr = <0x1d08008 0x4>;

			qcom,rx-irq-clr-mask = <0x2>;

			qcom,dev-name = "qsee_ipc_irq_spss";

			interrupts = <0 349 4>;

			label = "spss";

		};

	};

Documentation/devicetree/bindings/clock/qcom,aop-qmp.txt

+2 −2
Original line number Original line Diff line number Diff line
@@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Always On Processor Clock controller Binding 
------------------------------------------------------------------------

------------------------------------------------------------------------





Required properties :

Required properties :

- compatible : must be "qcom,aop-qmp-clk"

- compatible : must be "qcom,aop-qmp-clk-v1" or "qcom,aop-qmp-clk-v2".

- #clock-cells : must contain 1

- #clock-cells : must contain 1

- mboxes : list of QMP mailbox phandle and channel identifier tuples.

- mboxes : list of QMP mailbox phandle and channel identifier tuples.

- mbox-names: List of identifier strings for each mailbox channel.

- mbox-names: List of identifier strings for each mailbox channel.
@@ -10,7 +10,7 @@ Required properties : 




Example :

Example :

	clock_qdss: qcom,aopclk {

	clock_qdss: qcom,aopclk {

		compatible = "qcom,aop-qmp-clk";

		compatible = "qcom,aop-qmp-clk-v1";

		#clock-cells = <1>;

		#clock-cells = <1>;

		mboxes = <&qmp_aop 0>;

		mboxes = <&qmp_aop 0>;

		mbox-names = "qdss_clk";

		mbox-names = "qdss_clk";

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+3 −1
Original line number Original line Diff line number Diff line
@@ -4,7 +4,9 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding 
Required properties :

Required properties :

- compatible : shall contain only one of the following:

- compatible : shall contain only one of the following:

		"qcom,gpucc-sdm845",

		"qcom,gpucc-sdm845",

		"qcom,gfxcc-sdm845"

		"qcom,gpucc-sdm845-v2",

		"qcom,gfxcc-sdm845",

		"qcom,gfxcc-sdm845-v2"





- reg : shall contain base register offset and size.

- reg : shall contain base register offset and size.

- #clock-cells : shall contain 1.

- #clock-cells : shall contain 1.