Commit 6a1c5312 authored Apr 27, 2012 by Will Deacon Committed by Russell King Apr 28, 2012

ARM: 7403/1: tls: remove covert channel via TPIDRURW



TPIDRURW is a user read/write register forming part of the group of
thread registers in more recent versions of the ARM architecture (~v6+).

Currently, the kernel does not touch this register, which allows tasks
to communicate covertly by reading and writing to the register without
context-switching affecting its contents.

This patch clears TPIDRURW when TPIDRURO is updated via the set_tls
macro, which is called directly from __switch_to. Since the current
behaviour makes the register useless to userspace as far as thread
pointers are concerned, simply clearing the register (rather than saving
and restoring it) will not cause any problems to userspace.

Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent 14904927

arch/arm/include/asm/tls.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,8 @@

		.macro set_tls_v6k, tp, tmp1, tmp2
		mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
		mov \tmp1, #0
		mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
		.endm

		.macro set_tls_v6, tp, tmp1, tmp2
		@@ -15,6 +17,8 @@
		mov \tmp2, #0xffff0fff
		tst \tmp1, #HWCAP_TLS @ hardware TLS available?
		mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
		movne \tmp1, #0
		mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
		streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
		.endm