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Commit 6a0e2430 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
Browse files

[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation 



Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent d11d9b2d

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ menu "System Type" 


choice

	prompt "ARM system type"

	default ARCH_RPC

	default ARCH_VERSATILE



config ARCH_CLPS7500

	bool "Cirrus-CL-PS7500FE"

arch/arm/mm/tlb-v6.S

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) 
	add	r0, r0, #PAGE_SZ

	cmp	r0, r1

	blo	1b

	mcr	p15, 0, r2, c7, c10, 4		@ data synchronization barrier

	mov	pc, lr



	.section ".text.init", #alloc, #execinstr

include/asm-arm/tlbflush.h

+6 −0
Original line number Diff line number Diff line
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 
		asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));

	if (tlb_flag(TLB_V6_I_PAGE))

		asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));



	/* The ARM ARM states that the completion of a TLB maintenance

	 * operation is only guaranteed by a DSB instruction

	 */

	if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))

		asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));

}



/*