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Commit 69ec4cc6 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: Add support for dspp pa memcolor features"

parents b2ec613d 7b8fbae9

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -208,6 +208,8 @@ 
		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x0 0x00030001>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-memcolor = <0x880 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-gamut = <0x1000 0x00040000>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

drivers/gpu/drm/msm/sde/sde_color_processing.c

+97 −4
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ static void dspp_pcc_install_property(struct drm_crtc *crtc); 


static void dspp_hsic_install_property(struct drm_crtc *crtc);



static void dspp_memcolor_install_property(struct drm_crtc *crtc);



static void dspp_sixzone_install_property(struct drm_crtc *crtc);



static void dspp_ad_install_property(struct drm_crtc *crtc);



static void dspp_vlut_install_property(struct drm_crtc *crtc);
@@ -85,6 +89,8 @@ static void sde_cp_notify_hist_event(struct drm_crtc *crtc_drm, void *arg); 
do { \

	func[SDE_DSPP_PCC] = dspp_pcc_install_property; \

	func[SDE_DSPP_HSIC] = dspp_hsic_install_property; \

	func[SDE_DSPP_MEMCOLOR] = dspp_memcolor_install_property; \

	func[SDE_DSPP_SIXZONE] = dspp_sixzone_install_property; \

	func[SDE_DSPP_AD] = dspp_ad_install_property; \

	func[SDE_DSPP_VLUT] = dspp_vlut_install_property; \

	func[SDE_DSPP_GAMUT] = dspp_gamut_install_property; \
@@ -109,7 +115,10 @@ enum { 
	SDE_CP_CRTC_DSPP_PCC,

	SDE_CP_CRTC_DSPP_GC,

	SDE_CP_CRTC_DSPP_HSIC,

	SDE_CP_CRTC_DSPP_MEMCOLOR,

	SDE_CP_CRTC_DSPP_MEMCOL_SKIN,

	SDE_CP_CRTC_DSPP_MEMCOL_SKY,

	SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,

	SDE_CP_CRTC_DSPP_MEMCOL_PROT,

	SDE_CP_CRTC_DSPP_SIXZONE,

	SDE_CP_CRTC_DSPP_GAMUT,

	SDE_CP_CRTC_DSPP_DITHER,
@@ -671,12 +680,33 @@ static void sde_cp_crtc_setfeature(struct sde_cp_node *prop_node, 
			}

			hw_dspp->ops.setup_pa_hsic(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_MEMCOLOR:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcolor) {

		case SDE_CP_CRTC_DSPP_MEMCOL_SKIN:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_skin) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_pa_memcol_skin(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_MEMCOL_SKY:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_sky) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_pa_memcolor(hw_dspp, &hw_cfg);

			hw_dspp->ops.setup_pa_memcol_sky(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_foliage) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_pa_memcol_foliage(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_MEMCOL_PROT:

			if (!hw_dspp || !hw_dspp->ops.setup_pa_memcol_prot) {

				ret = -EINVAL;

				continue;

			}

			hw_dspp->ops.setup_pa_memcol_prot(hw_dspp, &hw_cfg);

			break;

		case SDE_CP_CRTC_DSPP_SIXZONE:

			if (!hw_dspp || !hw_dspp->ops.setup_sixzone) {
@@ -1200,6 +1230,69 @@ static void dspp_hsic_install_property(struct drm_crtc *crtc) 
	}

}



static void dspp_memcolor_install_property(struct drm_crtc *crtc)

{

	char feature_name[256];

	struct sde_kms *kms = NULL;

	struct sde_mdss_cfg *catalog = NULL;

	u32 version;



	kms = get_kms(crtc);

	catalog = kms->catalog;

	version = catalog->dspp[0].sblk->memcolor.version >> 16;

	switch (version) {

	case 1:

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_MEMCOL_SKIN_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_MEMCOL_SKIN,

			sizeof(struct drm_msm_memcol));

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_MEMCOL_SKY_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_MEMCOL_SKY,

			sizeof(struct drm_msm_memcol));

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_MEMCOL_FOLIAGE_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_MEMCOL_FOLIAGE,

			sizeof(struct drm_msm_memcol));

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_MEMCOL_PROT_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_MEMCOL_PROT,

			sizeof(struct drm_msm_memcol));

		break;

	default:

		DRM_ERROR("version %d not supported\n", version);

		break;

	}

}



static void dspp_sixzone_install_property(struct drm_crtc *crtc)

{

	char feature_name[256];

	struct sde_kms *kms = NULL;

	struct sde_mdss_cfg *catalog = NULL;

	u32 version;



	kms = get_kms(crtc);

	catalog = kms->catalog;

	version = catalog->dspp[0].sblk->sixzone.version >> 16;

	switch (version) {

	case 1:

		snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d",

			"SDE_DSPP_PA_SIXZONE_V", version);

		sde_cp_crtc_install_blob_property(crtc, feature_name,

			SDE_CP_CRTC_DSPP_SIXZONE,

			sizeof(struct drm_msm_sixzone));

		break;

	default:

		DRM_ERROR("version %d not supported\n", version);

		break;

	}

}



static void dspp_vlut_install_property(struct drm_crtc *crtc)

{

	char feature_name[256];

drivers/gpu/drm/msm/sde/sde_color_processing.h

+2 −1
Original line number Diff line number Diff line
@@ -26,7 +26,8 @@ struct sde_irq_callback; 
enum sde_memcolor_type {

	MEMCOLOR_SKIN = 0,

	MEMCOLOR_SKY,

	MEMCOLOR_FOLIAGE

	MEMCOLOR_FOLIAGE,

	MEMCOLOR_MAX

};



/*

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+11 −1
Original line number Diff line number Diff line
@@ -72,6 +72,10 @@ enum { 
#define PA_VAL_EN BIT(27)

#define PA_CONT_EN BIT(28)



#define PA_SIXZONE_HUE_EN BIT(29)

#define PA_SIXZONE_SAT_EN BIT(30)

#define PA_SIXZONE_VAL_EN BIT(31)



#define PA_HIST_EN BIT(16)



#define PA_SKIN_EN BIT(7)
@@ -87,11 +91,17 @@ enum { 
#define PA_SAT_OFF 0x20

#define PA_VAL_OFF 0x24

#define PA_CONT_OFF 0x28

#define PA_PWL_HOLD_OFF 0x40



#define PA_DISABLE_REQUIRED(x) \

	!((x) & (PA_SKIN_EN | PA_SKY_EN | \

	PA_FOL_EN | PA_HUE_EN | \

	PA_SAT_EN | PA_VAL_EN | \

	PA_CONT_EN | PA_HIST_EN))

	PA_CONT_EN | PA_HIST_EN | \

	PA_SIXZONE_HUE_EN | PA_SIXZONE_SAT_EN | \

	PA_SIXZONE_VAL_EN))



#define SIXZONE_ADJ_CURVE_P1_OFF 0x4

#define SIXZONE_THRESHOLDS_OFF 0x8



#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_color_processing_v1_7.c

+317 −2
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#include "sde_hw_color_processing_v1_7.h"

#include "sde_hw_ctl.h"



#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))



#define PA_HUE_VIG_OFF		0x110

#define PA_SAT_VIG_OFF		0x114

#define PA_VAL_VIG_OFF		0x118
@@ -78,18 +80,44 @@ 
#define DSPP_OP_PA_FOL_EN	BIT(6)

#define DSPP_OP_PA_SKY_EN	BIT(7)



#define DSPP_SZ_ADJ_CURVE_P1_OFF	0x4

#define DSPP_SZ_THRESHOLDS_OFF	0x8

#define DSPP_PA_PWL_HOLD_OFF	0x40



#define DSPP_MEMCOL_SIZE0	0x14

#define DSPP_MEMCOL_SIZE1	0x8

#define DSPP_MEMCOL_PWL0_OFF	0x0

#define DSPP_MEMCOL_PWL2_OFF	0x3C

#define DSPP_MEMCOL_HOLD_SIZE	0x4



#define DSPP_MEMCOL_PROT_VAL_EN BIT(24)

#define DSPP_MEMCOL_PROT_SAT_EN BIT(23)

#define DSPP_MEMCOL_PROT_HUE_EN BIT(22)

#define DSPP_MEMCOL_PROT_CONT_EN BIT(18)

#define DSPP_MEMCOL_PROT_SIXZONE_EN BIT(17)

#define DSPP_MEMCOL_PROT_BLEND_EN BIT(3)



#define DSPP_MEMCOL_MASK \

	(DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | DSPP_OP_PA_FOL_EN)



#define DSPP_MEMCOL_PROT_MASK \

	(DSPP_MEMCOL_PROT_HUE_EN | DSPP_MEMCOL_PROT_SAT_EN | \

	DSPP_MEMCOL_PROT_VAL_EN | DSPP_MEMCOL_PROT_CONT_EN | \

	DSPP_MEMCOL_PROT_SIXZONE_EN | DSPP_MEMCOL_PROT_BLEND_EN)



#define PA_VIG_DISABLE_REQUIRED(x) \

			!((x) & (VIG_OP_PA_SKIN_EN | VIG_OP_PA_SKY_EN | \

			VIG_OP_PA_FOL_EN | VIG_OP_PA_HUE_EN | \

			VIG_OP_PA_SAT_EN | VIG_OP_PA_VAL_EN | \

			VIG_OP_PA_CONT_EN))





#define PA_DSPP_DISABLE_REQUIRED(x) \

			!((x) & (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_SKY_EN | \

			DSPP_OP_PA_FOL_EN | DSPP_OP_PA_HUE_EN | \

			DSPP_OP_PA_SAT_EN | DSPP_OP_PA_VAL_EN | \

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN))

			DSPP_OP_PA_CONT_EN | DSPP_OP_PA_HIST_EN | \

			DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN | \

			DSPP_OP_SZ_VAL_EN))



#define DSPP_OP_PCC_ENABLE	BIT(0)

#define PCC_OP_MODE_OFF		0
@@ -293,6 +321,79 @@ void sde_setup_dspp_pa_hsic_v17(struct sde_hw_dspp *ctx, void *cfg) 
	__setup_pa_cont(&ctx->hw, &ctx->cap->sblk->hsic, cont, DSPP);

}



void sde_setup_dspp_sixzone_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_sixzone *sixzone;

	u32 opcode = 0, local_opcode = 0;

	u32 reg = 0, hold = 0, local_hold = 0;

	u32 addr = 0;

	int i = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable sixzone feature\n");

		opcode &= ~(DSPP_OP_SZ_HUE_EN | DSPP_OP_SZ_SAT_EN |

			DSPP_OP_SZ_VAL_EN);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_sixzone)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_sixzone));

		return;

	}



	sixzone = hw_cfg->payload;



	reg = BIT(26);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->sixzone.base, reg);



	addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_ADJ_CURVE_P1_OFF;

	for (i = 0; i < SIXZONE_LUT_SIZE; i++) {

		SDE_REG_WRITE(&ctx->hw, addr, sixzone->curve[i].p1);

		SDE_REG_WRITE(&ctx->hw, (addr - 4), sixzone->curve[i].p0);

	}



	addr = ctx->cap->sblk->sixzone.base + DSPP_SZ_THRESHOLDS_OFF;

	SDE_REG_WRITE(&ctx->hw, addr, sixzone->threshold);

	SDE_REG_WRITE(&ctx->hw, (addr + 4), sixzone->adjust_p0);

	SDE_REG_WRITE(&ctx->hw, (addr + 8), sixzone->adjust_p1);



	hold = SDE_REG_READ(&ctx->hw,

		(ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF));

	local_hold = ((sixzone->sat_hold & REG_MASK(2)) << 12);

	local_hold |= ((sixzone->val_hold & REG_MASK(2)) << 14);

	hold &= ~REG_MASK_SHIFT(4, 12);

	hold |= local_hold;

	SDE_REG_WRITE(&ctx->hw,

		(ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF),

		hold);



	if (sixzone->flags & SIXZONE_HUE_ENABLE)

		local_opcode |= DSPP_OP_SZ_HUE_EN;

	if (sixzone->flags & SIXZONE_SAT_ENABLE)

		local_opcode |= DSPP_OP_SZ_SAT_EN;

	if (sixzone->flags & SIXZONE_VAL_ENABLE)

		local_opcode |= DSPP_OP_SZ_VAL_EN;



	if (local_opcode)

		local_opcode |= DSPP_OP_PA_EN;



	opcode &= ~REG_MASK_SHIFT(3, 29);

	opcode |= local_opcode;

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

}



void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx,

				   enum sde_memcolor_type type,

				   void *cfg)
@@ -356,6 +457,220 @@ void sde_setup_pipe_pa_memcol_v1_7(struct sde_hw_pipe *ctx, 
	SDE_REG_WRITE(&ctx->hw, base, op);

}



static void __setup_dspp_memcol(struct sde_hw_dspp *ctx,

		enum sde_memcolor_type type,

		struct drm_msm_memcol *memcolor)

{

	u32 addr = 0, offset = 0, idx = 0;

	u32 hold = 0, local_hold = 0, hold_shift = 0;



	switch (type) {

	case MEMCOLOR_SKIN:

		idx = 0;

		break;

	case MEMCOLOR_SKY:

		idx = 1;

		break;

	case MEMCOLOR_FOLIAGE:

		idx = 2;

		break;

	default:

		DRM_ERROR("Invalid memory color type %d\n", type);

		return;

	}



	offset = DSPP_MEMCOL_PWL0_OFF + (idx * DSPP_MEMCOL_SIZE0);

	addr = ctx->cap->sblk->memcolor.base + offset;

	hold_shift = idx * DSPP_MEMCOL_HOLD_SIZE;



	SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p0);

	addr += 4;

	SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p1);

	addr += 4;

	SDE_REG_WRITE(&ctx->hw, addr, memcolor->hue_region);

	addr += 4;

	SDE_REG_WRITE(&ctx->hw, addr, memcolor->sat_region);

	addr += 4;

	SDE_REG_WRITE(&ctx->hw, addr, memcolor->val_region);



	offset = DSPP_MEMCOL_PWL2_OFF + (idx * DSPP_MEMCOL_SIZE1);

	addr = ctx->cap->sblk->memcolor.base + offset;



	SDE_REG_WRITE(&ctx->hw, addr, memcolor->color_adjust_p2);

	addr += 4;

	SDE_REG_WRITE(&ctx->hw, addr, memcolor->blend_gain);



	addr = ctx->cap->sblk->hsic.base + DSPP_PA_PWL_HOLD_OFF;

	hold = SDE_REG_READ(&ctx->hw, addr);

	local_hold = ((memcolor->sat_hold & REG_MASK(2)) << hold_shift);

	local_hold |=

		((memcolor->val_hold & REG_MASK(2)) << (hold_shift + 2));

	hold &= ~REG_MASK_SHIFT(4, hold_shift);

	hold |= local_hold;

	SDE_REG_WRITE(&ctx->hw, addr, hold);

}



void sde_setup_dspp_memcol_skin_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_memcol *memcolor;

	u32 opcode = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable memcolor skin feature\n");

		opcode &= ~(DSPP_OP_PA_SKIN_EN);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_memcol));

		return;

	}



	memcolor = hw_cfg->payload;



	__setup_dspp_memcol(ctx, MEMCOLOR_SKIN, memcolor);



	opcode |= (DSPP_OP_PA_SKIN_EN | DSPP_OP_PA_EN);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

}



void sde_setup_dspp_memcol_sky_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_memcol *memcolor;

	u32 opcode = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable memcolor sky feature\n");

		opcode &= ~(DSPP_OP_PA_SKY_EN);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_memcol));

		return;

	}



	memcolor = hw_cfg->payload;



	__setup_dspp_memcol(ctx, MEMCOLOR_SKY, memcolor);



	opcode |= (DSPP_OP_PA_SKY_EN | DSPP_OP_PA_EN);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

}



void sde_setup_dspp_memcol_foliage_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_memcol *memcolor;

	u32 opcode = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable memcolor foliage feature\n");

		opcode &= ~(DSPP_OP_PA_FOL_EN);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_memcol));

		return;

	}



	memcolor = hw_cfg->payload;



	__setup_dspp_memcol(ctx, MEMCOLOR_FOLIAGE, memcolor);



	opcode |= (DSPP_OP_PA_FOL_EN | DSPP_OP_PA_EN);

	SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

}



void sde_setup_dspp_memcol_prot_v17(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_memcol *memcolor;

	u32 opcode = 0, local_opcode = 0;



	if (!ctx || !cfg) {

		DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);

		return;

	}



	opcode = SDE_REG_READ(&ctx->hw, ctx->cap->sblk->hsic.base);



	if (!hw_cfg->payload) {

		DRM_DEBUG_DRIVER("disable memcolor prot feature\n");

		opcode &= ~(DSPP_MEMCOL_PROT_MASK);

		if (PA_DSPP_DISABLE_REQUIRED(opcode))

			opcode &= ~DSPP_OP_PA_EN;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

		return;

	}



	if (hw_cfg->len != sizeof(struct drm_msm_memcol)) {

		DRM_ERROR("invalid size of payload len %d exp %zd\n",

			hw_cfg->len, sizeof(struct drm_msm_memcol));

		return;

	}



	memcolor = hw_cfg->payload;



	if (memcolor->prot_flags) {

		if (memcolor->prot_flags & MEMCOL_PROT_HUE)

			local_opcode |= DSPP_MEMCOL_PROT_HUE_EN;

		if (memcolor->prot_flags & MEMCOL_PROT_SAT)

			local_opcode |= DSPP_MEMCOL_PROT_SAT_EN;

		if (memcolor->prot_flags & MEMCOL_PROT_VAL)

			local_opcode |= DSPP_MEMCOL_PROT_VAL_EN;

		if (memcolor->prot_flags & MEMCOL_PROT_CONT)

			local_opcode |= DSPP_MEMCOL_PROT_CONT_EN;

		if (memcolor->prot_flags & MEMCOL_PROT_SIXZONE)

			local_opcode |= DSPP_MEMCOL_PROT_SIXZONE_EN;

		if (memcolor->prot_flags & MEMCOL_PROT_BLEND)

			local_opcode |= DSPP_MEMCOL_PROT_BLEND_EN;

	}



	if (local_opcode) {

		local_opcode |= DSPP_OP_PA_EN;

		opcode &= ~(DSPP_MEMCOL_PROT_MASK);

		opcode |= local_opcode;

		SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->hsic.base, opcode);

	}

}



void sde_setup_dspp_pcc_v1_7(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;