Commit 69e20e78 authored Jan 19, 2018 by Blagovest Kolenichev

Merge android-4.9-o.76 (bdc34d94) into msm-4.9



* refs/heads/tmp-bdc34d94:
  Linux 4.9.76
  mtd: nand: pxa3xx: Fix READOOB implementation
  Map the vsyscall page with _PAGE_USER
  x86/tlb: Drop the _GPL from the cpu_tlbstate export
  parisc: qemu idle sleep support
  parisc: Fix alignment of pa_tlb_lock in assembly on 32-bit SMP kernel
  x86/microcode/AMD: Add support for fam17h microcode loading
  Input: elantech - add new icbody type 15
  ARC: uaccess: dont use "l" gcc inline asm constraint modifier
  iommu/arm-smmu-v3: Cope with duplicated Stream IDs
  iommu/arm-smmu-v3: Don't free page table ops twice
  kernel/signal.c: remove the no longer needed SIGNAL_UNKILLABLE check in complete_signal()
  kernel/signal.c: protect the SIGNAL_UNKILLABLE tasks from !sig_kernel_only() signals
  kernel/signal.c: protect the traced SIGNAL_UNKILLABLE tasks from SIGKILL
  kernel: make groups_sort calling a responsibility group_info allocators
  nbd: fix use-after-free of rq/bio in the xmit path
  fscache: Fix the default for fscache_maybe_release_page()
  sunxi-rsb: Include OF based modalias in device uevent
  crypto: pcrypt - fix freeing pcrypt instances
  crypto: chacha20poly1305 - validate the digest size
  crypto: n2 - cure use after free
  kernel/acct.c: fix the acct->needcheck check in check_free_space()
  clocksource: arch_timer: make virtual counter access configurable
  arm64: issue isb when trapping CNTVCT_EL0 access
  BACKPORT: arm64: Add CNTFRQ_EL0 trap handler
  BACKPORT: arm64: Add CNTVCT_EL0 trap handler
  ANDROID: arm64: kaslr: fixup Falkor workaround for 4.9
  arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry
  arm64: use RET instruction for exiting the trampoline
  UPSTREAM: arm64: kaslr: Put kernel vectors address in separate data page
  UPSTREAM: arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR
  UPSTREAM: arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0
  UPSTREAM: arm64: entry: Add fake CPU feature for unmapping the kernel at EL0
  UPSTREAM: arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks
  UPSTREAM: arm64: erratum: Work around Falkor erratum #E1003 in trampoline code
  UPSTREAM: arm64: entry: Hook up entry trampoline to exception vectors
  UPSTREAM: arm64: entry: Explicitly pass exception level to kernel_ventry macro
  UPSTREAM: arm64: mm: Map entry trampoline into trampoline and kernel page tables
  UPSTREAM: arm64: entry: Add exception trampoline page for exceptions from EL0
  UPSTREAM: arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI
  UPSTREAM: arm64: mm: Add arm64_kernel_unmapped_at_el0 helper
  UPSTREAM: arm64: mm: Allocate ASIDs in pairs
  UPSTREAM: arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN
  UPSTREAM: arm64: mm: Rename post_ttbr0_update_workaround
  UPSTREAM: arm64: mm: Move ASID from TTBR0 to TTBR1
  UPSTREAM: arm64: mm: Temporarily disable ARM64_SW_TTBR0_PAN
  UPSTREAM: arm64: mm: Use non-global mappings for kernel space
  UPSTREAM: arm64: factor out entry stack manipulation

Conflicts:
	arch/arm64/Kconfig
	arch/arm64/include/asm/assembler.h
	arch/arm64/include/asm/cpucaps.h
	arch/arm64/include/asm/mmu.h
	arch/arm64/kernel/cpufeature.c
	arch/arm64/kernel/entry.S
	arch/arm64/mm/proc.S

Change-Id: I2580cc0b3d68f67e0da6934dbb6d22e313a1abe5
Signed-off-by: Blagovest Kolenichev <bkolenichev@codeaurora.org>

parents 5d703979 bdc34d94

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 4
		PATCHLEVEL = 9
		SUBLEVEL = 75
		SUBLEVEL = 76
		EXTRAVERSION =
		NAME = Roaring Lionus

arch/arc/include/asm/uaccess.h

+3 −2

Original line number	Diff line number	Diff line
		@@ -673,6 +673,7 @@ __arc_strncpy_from_user(char dst, const char __user src, long count)
		return 0;

		__asm__ __volatile__(
		" mov lp_count, %5 \n"
		" lp 3f \n"
		"1: ldb.ab %3, [%2, 1] \n"
		" breq.d %3, 0, 3f \n"
		@@ -689,8 +690,8 @@ __arc_strncpy_from_user(char dst, const char __user src, long count)
		" .word 1b, 4b \n"
		" .previous \n"
		: "+r"(res), "+r"(dst), "+r"(src), "=r"(val)
		: "g"(-EFAULT), "l"(count)
		: "memory");
		: "g"(-EFAULT), "r"(count)
		: "lp_count", "lp_start", "lp_end", "memory");

		return res;
		}

arch/parisc/include/asm/ldcw.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -11,6 +11,7 @@
		for the semaphore. */

		#define __PA_LDCW_ALIGNMENT 16
		#define __PA_LDCW_ALIGN_ORDER 4
		#define __ldcw_align(a) ({ \
		unsigned long __ret = (unsigned long) &(a)->lock[0]; \
		__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) \
		@@ -28,6 +29,7 @@
		ldcd). */

		#define __PA_LDCW_ALIGNMENT 4
		#define __PA_LDCW_ALIGN_ORDER 2
		#define __ldcw_align(a) (&(a)->slock)
		#define __LDCW "ldcw,co"

arch/parisc/kernel/entry.S

+11 −2

Original line number	Diff line number	Diff line
		@@ -35,6 +35,7 @@
		#include <asm/pgtable.h>
		#include <asm/signal.h>
		#include <asm/unistd.h>
		#include <asm/ldcw.h>
		#include <asm/thread_info.h>

		#include <linux/linkage.h>
		@@ -46,6 +47,14 @@
		#endif

		.import pa_tlb_lock,data
		.macro load_pa_tlb_lock reg
		#if __PA_LDCW_ALIGNMENT > 4
		load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
		depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
		#else
		load32 PA(pa_tlb_lock), \reg
		#endif
		.endm

		/* space_to_prot macro creates a prot id from a space id */

		@@ -457,7 +466,7 @@
		.macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
		#ifdef CONFIG_SMP
		cmpib,COND(=),n 0,\spc,2f
		load32 PA(pa_tlb_lock),\tmp
		load_pa_tlb_lock \tmp
		1: LDCW 0(\tmp),\tmp1
		cmpib,COND(=) 0,\tmp1,1b
		nop
		@@ -480,7 +489,7 @@
		/* Release pa_tlb_lock lock. */
		.macro tlb_unlock1 spc,tmp
		#ifdef CONFIG_SMP
		load32 PA(pa_tlb_lock),\tmp
		load_pa_tlb_lock \tmp
		tlb_unlock0 \spc,\tmp
		#endif
		.endm

arch/parisc/kernel/pacache.S

+7 −2

Original line number	Diff line number	Diff line
		@@ -36,6 +36,7 @@
		#include <asm/assembly.h>
		#include <asm/pgtable.h>
		#include <asm/cache.h>
		#include <asm/ldcw.h>
		#include <linux/linkage.h>

		.text
		@@ -333,8 +334,12 @@ ENDPROC_CFI(flush_data_cache_local)

		.macro tlb_lock la,flags,tmp
		#ifdef CONFIG_SMP
		ldil L%pa_tlb_lock,%r1
		ldo R%pa_tlb_lock(%r1),\la
		#if __PA_LDCW_ALIGNMENT > 4
		load32 pa_tlb_lock + __PA_LDCW_ALIGNMENT-1, \la
		depi 0,31,__PA_LDCW_ALIGN_ORDER, \la
		#else
		load32 pa_tlb_lock, \la
		#endif
		rsm PSW_SM_I,\flags
		1: LDCW 0(\la),\tmp
		cmpib,<>,n 0,\tmp,3f