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Commit 69d8e1e8 authored by Robert Richter's avatar Robert Richter Committed by Ingo Molnar
Browse files

perf, x86: Add new AMD family 15h msrs to perfctr reservation code 



This patch allows the reservation of perfctrs with new msr addresses
introduced for AMD cpu family 15h (0xc0010200/0xc0010201, etc).

Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <1296664860-10886-4-git-send-email-robert.richter@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 41bf4989

arch/x86/kernel/cpu/perfctr-watchdog.c

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) 
	/* returns the bit offset of the performance counter register */

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_AMD:

		if (msr >= MSR_F15H_PERF_CTR)

			return (msr - MSR_F15H_PERF_CTR) >> 1;

		return msr - MSR_K7_PERFCTR0;

	case X86_VENDOR_INTEL:

		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
@@ -70,6 +72,8 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) 
	/* returns the bit offset of the event selection register */

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_AMD:

		if (msr >= MSR_F15H_PERF_CTL)

			return (msr - MSR_F15H_PERF_CTL) >> 1;

		return msr - MSR_K7_EVNTSEL0;

	case X86_VENDOR_INTEL:

		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))