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Commit 69bbeb4a authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values 



The DDL registers can hold 7bit numbers. Make the most of those seven
bits by adjusting the threshold where we switch between the 64 vs. 32
precision multipliers.

Also we compute 'entries' to make the decision about precision, and then
we recompute the same value to calculate the actual drain latency. Just
use the already calculate 'entries' there.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 22c5aee3

drivers/gpu/drm/i915/intel_pm.c

+4 −5
Original line number Diff line number Diff line
@@ -1287,15 +1287,14 @@ static bool vlv_compute_drain_latency(struct drm_device *dev, 
	pixel_size = crtc->primary->fb->bits_per_pixel / 8;	/* BPP */



	entries = (clock / 1000) * pixel_size;

	*plane_prec_mult = (entries > 256) ?

	*plane_prec_mult = (entries > 128) ?

		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;

	*plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *

						     pixel_size);

	*plane_dl = (64 * (*plane_prec_mult) * 4) / entries;



	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */

	*cursor_prec_mult = (entries > 256) ?

	*cursor_prec_mult = (entries > 128) ?

		DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32;

	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);

	*cursor_dl = (64 * (*cursor_prec_mult) * 4) / entries;



	return true;

}