Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 69ba1ca9 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Add support to control the GCC_GPU_IREF_EN signal 



The gcc_gpu_iref_clk will be controlled by the GPU driver.
Add the programming support for it and provide the clock
handle to be used.

Change-Id: I0f4270083c6c43cb2938070cec83f3be35921261
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent ff3d7de3

drivers/clk/qcom/gcc-sdm845.c

+14 −0
Original line number Diff line number Diff line
@@ -1698,6 +1698,19 @@ static struct clk_gate2 gcc_gpu_gpll0_div_clk_src = { 
	},

};



static struct clk_branch gcc_gpu_iref_clk = {

	.halt_reg = 0x8c010,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x8c010,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_gpu_iref_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_gpu_memnoc_gfx_clk = {

	.halt_reg = 0x7100c,

	.halt_check = BRANCH_VOTED,
@@ -3310,6 +3323,7 @@ static struct clk_regmap *gcc_sdm845_clocks[] = { 
	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,

	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,

	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,

	[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,

	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,

	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,

	[GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,

include/dt-bindings/clock/qcom,gcc-sdm845.h

+1 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ 
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			179

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				180

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				181

#define GCC_GPU_IREF_CLK					182



/* GCC reset clocks */

#define GCC_GPU_BCR						0