Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 69aff2fd authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
Browse files

clk: exynos4: Add missing sclk_audio0 clock



This clock is a parent of mout_spdif and sclk_pcm0.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 4c3cc72c
Loading
Loading
Loading
Loading
+2 −0
Original line number Diff line number Diff line
@@ -508,6 +508,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
			CLK_SET_RATE_PARENT, 0),
	GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
			SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
	GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
			CLK_SET_RATE_PARENT, 0),
	GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
			CLK_SET_RATE_PARENT, 0),
	GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),