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Commit 692d2c9a authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: add pinctrl for SDM845"

parents 1b056a9c c1e83dc3

Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ SDM845 platform. 
- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sdm845-pinctrl"

	Definition: must be "qcom,sdm845-pinctrl" or "qcom,sdm845-pinctrl-v2"



- reg:

	Usage: required

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ 
/delete-node/ &apc0_cpr;

/delete-node/ &apc1_cpr;



&tlmm {

	compatible = "qcom,sdm845-pinctrl-v2";

};



&soc {

	/* CPR controller regulators */

	apc0_cpr: cprh-ctrl@17dc0000 {

drivers/pinctrl/qcom/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -16,6 +16,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o 
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o

obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o

obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o

obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o

obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o pinctrl-sdm845-v2.o

obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o

obj-$(CONFIG_PINCTRL_SDXPOORWILLS)	+= pinctrl-sdxpoorwills.o

drivers/pinctrl/qcom/pinctrl-msm.c

+51 −94
Original line number Diff line number Diff line
@@ -39,7 +39,6 @@ 


#define MAX_NR_GPIO 300

#define PS_HOLD_OFFSET 0x820

#define STATUS_OFFSET 0x10



/**

 * struct msm_pinctrl - state for a pinctrl-msm device
@@ -72,35 +71,6 @@ struct msm_pinctrl { 
	void __iomem *regs;

};



static u32 msm_pinctrl_find_base(const struct msm_pinctrl *pctrl, u32 gpio_id)

{

	int i;

	u32 val;

	const struct msm_pinctrl_soc_data *soc_data = pctrl->soc;



	if (gpio_id >= soc_data->ngpios || !soc_data->pin_base)

		return 0;



	if (soc_data->pin_base[gpio_id])

		return soc_data->pin_base[gpio_id];



	for (i = 0; i < soc_data->n_tile_offsets; i++) {

		val = readl_relaxed(pctrl->regs +

			soc_data->tile_offsets[i] + STATUS_OFFSET

			+ soc_data->reg_size * gpio_id);

		if (val) {

			soc_data->pin_base[gpio_id] = soc_data->tile_offsets[i];

			return soc_data->tile_offsets[i];

		}

	}



	/* In the case that the soc_data does not support dynamic base

	 * detection, we return 0 here.

	 */

	WARN_ONCE(1, "%s:Dynamic base detection is not supported\n", __func__);

	return 0;

}



static int msm_get_groups_count(struct pinctrl_dev *pctldev)

{

	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -170,11 +140,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 
	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val, mask, base;

	u32 val, mask;

	int i;



	g = &pctrl->soc->groups[group];

	base = msm_pinctrl_find_base(pctrl, group);

	mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);



	for (i = 0; i < g->nfuncs; i++) {
@@ -187,10 +156,10 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 


	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->ctl_reg);

	val = readl(pctrl->regs + g->ctl_reg);

	val &= ~mask;

	val |= i << g->mux_bit;

	writel(val, pctrl->regs + base + g->ctl_reg);

	writel(val, pctrl->regs + g->ctl_reg);



	spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -255,16 +224,15 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, 
	unsigned arg;

	unsigned bit;

	int ret;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[group];

	base = msm_pinctrl_find_base(pctrl, group);



	ret = msm_config_reg(pctrl, g, param, &mask, &bit);

	if (ret < 0)

		return ret;



	val = readl(pctrl->regs + base + g->ctl_reg);

	val = readl(pctrl->regs + g->ctl_reg);

	arg = (val >> bit) & mask;



	/* Convert register value to pinconf value */
@@ -289,7 +257,7 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, 
		if (!arg)

			return -EINVAL;



		val = readl(pctrl->regs + base + g->io_reg);

		val = readl(pctrl->regs + g->io_reg);

		arg = !!(val & BIT(g->in_bit));

		break;

	case PIN_CONFIG_INPUT_ENABLE:
@@ -320,12 +288,11 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, 
	unsigned arg;

	unsigned bit;

	int ret;

	u32 val, base;

	u32 val;

	int i;



	g = &pctrl->soc->groups[group];



	base = msm_pinctrl_find_base(pctrl, group);

	for (i = 0; i < num_configs; i++) {

		param = pinconf_to_config_param(configs[i]);

		arg = pinconf_to_config_argument(configs[i]);
@@ -358,12 +325,12 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, 
		case PIN_CONFIG_OUTPUT:

			/* set output value */

			spin_lock_irqsave(&pctrl->lock, flags);

			val = readl(pctrl->regs + base + g->io_reg);

			val = readl(pctrl->regs + g->io_reg);

			if (arg)

				val |= BIT(g->out_bit);

			else

				val &= ~BIT(g->out_bit);

			writel(val, pctrl->regs + base + g->io_reg);

			writel(val, pctrl->regs + g->io_reg);

			spin_unlock_irqrestore(&pctrl->lock, flags);



			/* enable output */
@@ -386,10 +353,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, 
		}



		spin_lock_irqsave(&pctrl->lock, flags);

		val = readl(pctrl->regs + base + g->ctl_reg);

		val = readl(pctrl->regs + g->ctl_reg);

		val &= ~(mask << bit);

		val |= arg << bit;

		writel(val, pctrl->regs + base + g->ctl_reg);

		writel(val, pctrl->regs + g->ctl_reg);

		spin_unlock_irqrestore(&pctrl->lock, flags);

	}
@@ -414,16 +381,15 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 
	const struct msm_pingroup *g;

	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[offset];

	base = msm_pinctrl_find_base(pctrl, offset);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->ctl_reg);

	val = readl(pctrl->regs + g->ctl_reg);

	val &= ~BIT(g->oe_bit);

	writel(val, pctrl->regs + base + g->ctl_reg);

	writel(val, pctrl->regs + g->ctl_reg);



	spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -435,23 +401,22 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in 
	const struct msm_pingroup *g;

	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[offset];

	base = msm_pinctrl_find_base(pctrl, offset);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->io_reg);

	val = readl(pctrl->regs + g->io_reg);

	if (value)

		val |= BIT(g->out_bit);

	else

		val &= ~BIT(g->out_bit);

	writel(val, pctrl->regs + base + g->io_reg);

	writel(val, pctrl->regs + g->io_reg);



	val = readl(pctrl->regs + base + g->ctl_reg);

	val = readl(pctrl->regs + g->ctl_reg);

	val |= BIT(g->oe_bit);

	writel(val, pctrl->regs + base + g->ctl_reg);

	writel(val, pctrl->regs + g->ctl_reg);



	spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -462,12 +427,11 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 
{

	const struct msm_pingroup *g;

	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[offset];

	base = msm_pinctrl_find_base(pctrl, offset);



	val = readl(pctrl->regs + base + g->io_reg);

	val = readl(pctrl->regs + g->io_reg);

	return !!(val & BIT(g->in_bit));

}
@@ -476,19 +440,18 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 
	const struct msm_pingroup *g;

	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[offset];

	base = msm_pinctrl_find_base(pctrl, offset);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->io_reg);

	val = readl(pctrl->regs + g->io_reg);

	if (value)

		val |= BIT(g->out_bit);

	else

		val &= ~BIT(g->out_bit);

	writel(val, pctrl->regs + base + g->io_reg);

	writel(val, pctrl->regs + g->io_reg);



	spin_unlock_irqrestore(&pctrl->lock, flags);

}
@@ -508,7 +471,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, 
	int is_out;

	int drive;

	int pull;

	u32 ctl_reg, base;

	u32 ctl_reg;



	static const char * const pulls[] = {

		"no pull",
@@ -518,9 +481,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, 
	};



	g = &pctrl->soc->groups[offset];

	base = msm_pinctrl_find_base(pctrl, offset);



	ctl_reg = readl(pctrl->regs + base + g->ctl_reg);

	ctl_reg = readl(pctrl->regs + g->ctl_reg);



	is_out = !!(ctl_reg & BIT(g->oe_bit));

	func = (ctl_reg >> g->mux_bit) & 7;
@@ -579,21 +540,21 @@ static struct gpio_chip msm_gpio_template = { 
 */

static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,

					  const struct msm_pingroup *g,

					  struct irq_data *d, u32 base)

					  struct irq_data *d)

{

	int loop_limit = 100;

	unsigned val, val2, intstat;

	unsigned pol;



	do {

		val = readl(pctrl->regs + base + g->io_reg) & BIT(g->in_bit);

		val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);



		pol = readl(pctrl->regs + base + g->intr_cfg_reg);

		pol = readl(pctrl->regs + g->intr_cfg_reg);

		pol ^= BIT(g->intr_polarity_bit);

		writel(pol, pctrl->regs + base + g->intr_cfg_reg);

		writel(pol, pctrl->regs + g->intr_cfg_reg);



		val2 = readl(pctrl->regs + base + g->io_reg) & BIT(g->in_bit);

		intstat = readl(pctrl->regs + base + g->intr_status_reg);

		val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);

		intstat = readl(pctrl->regs + g->intr_status_reg);

		if (intstat || (val == val2))

			return;

	} while (loop_limit-- > 0);
@@ -607,16 +568,15 @@ static void msm_gpio_irq_mask(struct irq_data *d) 
	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[d->hwirq];

	base = msm_pinctrl_find_base(pctrl, d->hwirq);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->intr_cfg_reg);

	val = readl(pctrl->regs + g->intr_cfg_reg);

	val &= ~BIT(g->intr_enable_bit);

	writel(val, pctrl->regs + base + g->intr_cfg_reg);

	writel(val, pctrl->regs + g->intr_cfg_reg);



	clear_bit(d->hwirq, pctrl->enabled_irqs);
@@ -629,16 +589,15 @@ static void msm_gpio_irq_unmask(struct irq_data *d) 
	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[d->hwirq];

	base = msm_pinctrl_find_base(pctrl, d->hwirq);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->intr_cfg_reg);

	val = readl(pctrl->regs + g->intr_cfg_reg);

	val |= BIT(g->intr_enable_bit);

	writel(val, pctrl->regs + base + g->intr_cfg_reg);

	writel(val, pctrl->regs + g->intr_cfg_reg);



	set_bit(d->hwirq, pctrl->enabled_irqs);
@@ -651,22 +610,21 @@ static void msm_gpio_irq_ack(struct irq_data *d) 
	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[d->hwirq];

	base = msm_pinctrl_find_base(pctrl, d->hwirq);



	spin_lock_irqsave(&pctrl->lock, flags);



	val = readl(pctrl->regs + base + g->intr_status_reg);

	val = readl(pctrl->regs + g->intr_status_reg);

	if (g->intr_ack_high)

		val |= BIT(g->intr_status_bit);

	else

		val &= ~BIT(g->intr_status_bit);

	writel(val, pctrl->regs + base + g->intr_status_reg);

	writel(val, pctrl->regs + g->intr_status_reg);



	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))

		msm_gpio_update_dual_edge_pos(pctrl, g, d, base);

		msm_gpio_update_dual_edge_pos(pctrl, g, d);



	spin_unlock_irqrestore(&pctrl->lock, flags);

}
@@ -677,10 +635,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val, base;

	u32 val;



	g = &pctrl->soc->groups[d->hwirq];

	base = msm_pinctrl_find_base(pctrl, d->hwirq);



	spin_lock_irqsave(&pctrl->lock, flags);



	/*
@@ -692,17 +650,17 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
		clear_bit(d->hwirq, pctrl->dual_edge_irqs);



	/* Route interrupts to application cpu */

	val = readl(pctrl->regs + base + g->intr_target_reg);

	val = readl(pctrl->regs + g->intr_target_reg);

	val &= ~(7 << g->intr_target_bit);

	val |= g->intr_target_kpss_val << g->intr_target_bit;

	writel(val, pctrl->regs + base + g->intr_target_reg);

	writel(val, pctrl->regs + g->intr_target_reg);



	/* Update configuration for gpio.

	 * RAW_STATUS_EN is left on for all gpio irqs. Due to the

	 * internal circuitry of TLMM, toggling the RAW_STATUS

	 * could cause the INTR_STATUS to be set for EDGE interrupts.

	 */

	val = readl(pctrl->regs + base + g->intr_cfg_reg);

	val = readl(pctrl->regs + g->intr_cfg_reg);

	val |= BIT(g->intr_raw_status_bit);

	if (g->intr_detection_width == 2) {

		val &= ~(3 << g->intr_detection_bit);
@@ -750,10 +708,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 
	} else {

		BUG();

	}

	writel(val, pctrl->regs + base + g->intr_cfg_reg);

	writel(val, pctrl->regs + g->intr_cfg_reg);



	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))

		msm_gpio_update_dual_edge_pos(pctrl, g, d, base);

		msm_gpio_update_dual_edge_pos(pctrl, g, d);



	spin_unlock_irqrestore(&pctrl->lock, flags);
@@ -882,7 +840,7 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) 
	struct irq_chip *chip = irq_desc_get_chip(desc);

	int irq_pin;

	int handled = 0;

	u32 val, base;

	u32 val;

	int i;



	chained_irq_enter(chip, desc);
@@ -893,8 +851,7 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) 
	 */

	for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {

		g = &pctrl->soc->groups[i];

		base = msm_pinctrl_find_base(pctrl, i);

		val = readl(pctrl->regs + base + g->intr_status_reg);

		val = readl(pctrl->regs + g->intr_status_reg);

		if (val & BIT(g->intr_status_bit)) {

			irq_pin = irq_find_mapping(gc->irqdomain, i);

			generic_handle_irq(irq_pin);

drivers/pinctrl/qcom/pinctrl-msm.h

+0 −4
Original line number Diff line number Diff line
@@ -129,10 +129,6 @@ struct msm_pinctrl_soc_data { 
	unsigned ngpios;

	const struct msm_dir_conn *dir_conn;

	unsigned int n_dir_conns;

	const u32 *tile_offsets;

	unsigned int n_tile_offsets;

	u32 *pin_base;

	unsigned int reg_size;

};



int msm_pinctrl_probe(struct platform_device *pdev,