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Commit 690e6a0c authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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ARM: dts: msm: update DSI panel phy timings for SDM845 



The DSI panel phy timings binding is tuple that specifies 12 register
values. Current implementation only specifies 11 values for all the
supported panels on SDM845 which results in incorrect parsing of this
binding for these panels. Fix this by adding the missing register
configuration to this tuple of all the supported panels.

Change-Id: Ia90691757e190cc178d5c34ba31d30bc05eaa363
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent c6d522c5

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ Required properties: 
- qcom,mdss-dsi-panel-destination:	A string that specifies the destination display for the panel.

					"display_1" = DISPLAY_1

					"display_2" = DISPLAY_2

- qcom,mdss-dsi-panel-timings:		An array of length 12 that specifies the PHY

- qcom,mdss-dsi-panel-phy-timings:	An array of length 12 that specifies the PHY

					timing settings for the panel.

- qcom,mdss-dsi-panel-timings-8996:		An array of length 40 char that specifies the 8996 PHY lane

					timing settings for the panel.

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -296,43 +296,43 @@ 
};



&dsi_dual_nt35597_truly_video {

	qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x2D>;

};



&dsi_dual_nt35597_truly_cmd {

	qcom,mdss-dsi-panel-timings = [00 1c 07 07 23 21 07 07 05 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 07 05 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0D>;

	qcom,mdss-dsi-t-clk-pre = <0x2D>;

};



&dsi_nt35597_truly_dsc_cmd {

	qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0b>;

	qcom,mdss-dsi-t-clk-pre = <0x23>;

};



&dsi_nt35597_truly_dsc_video {

	qcom,mdss-dsi-panel-timings = [00 15 05 05 20 1f 05 05 03 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 05 03 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0b>;

	qcom,mdss-dsi-t-clk-pre = <0x23>;

};



&dsi_sharp_4k_dsc_video {

	qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 04 02 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0a>;

	qcom,mdss-dsi-t-clk-pre = <0x1e>;

};



&dsi_sharp_4k_dsc_cmd {

	qcom,mdss-dsi-panel-timings = [00 12 04 04 1e 1e 04 04 02 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 04 02 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0a>;

	qcom,mdss-dsi-t-clk-pre = <0x1e>;

};



&dsi_dual_sharp_1080_120hz_cmd {

	qcom,mdss-dsi-panel-timings = [00 24 09 09 26 24 09 09 06 03 04];

	qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 09 06 03 04 00];

	qcom,mdss-dsi-t-clk-post = <0x0f>;

	qcom,mdss-dsi-t-clk-pre = <0x36>;

};