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Commit 690c70ba authored by Ruchika Kharwar's avatar Ruchika Kharwar Committed by Felipe Balbi
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usb: phy: omap-usb3: fix dpll clock index 



Correction of the omap_usb3_dpll_params array when the sys_clk_rate is
20MHz.

Signed-off-by: default avatarNikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: default avatarRuchika Kharwar <ruchika@ti.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 24e6bfd9

drivers/usb/phy/phy-omap-usb3.c

+1 −1
Original line number Diff line number Diff line
@@ -71,9 +71,9 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = { 
	{1250, 5, 4, 20, 0},		/* 12 MHz */

	{3125, 20, 4, 20, 0},		/* 16.8 MHz */

	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */

	{1000, 7, 4, 10, 0},            /* 20 MHz */

	{1250, 12, 4, 20, 0},		/* 26 MHz */

	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */

	{1000, 7, 4, 10, 0},            /* 20 MHz */



};