Merge branches 'next/generic', 'next/alchemy', 'next/bcm63xx', 'next/cavium',...

* Compact Flash

The Cavium Compact Flash device is connected to the Octeon Boot Bus,

and is thus a child of the Boot Bus device.  It can read and write

industry standard compact flash devices.

Properties:

- compatible: "cavium,ebt3000-compact-flash";

  Compatibility with many Cavium evaluation boards.

- reg: The base address of the the CF chip select banks.  Depending on

  the device configuration, there may be one or two banks.

- cavium,bus-width: The width of the connection to the CF devices.  Valid

  values are 8 and 16.

- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.

- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected

  to this device.

Example:

	compact-flash@5,0 {

		compatible = "cavium,ebt3000-compact-flash";

		reg = <5 0 0x10000>, <6 0 0x10000>;

		cavium,bus-width = <16>;

		cavium,true-ide;

		cavium,dma-engine-handle = <&dma0>;

	};

* General Purpose Input Output (GPIO) bus.

Properties:

- compatible: "cavium,octeon-3860-gpio"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the GPIO unit's register bank.

- gpio-controller: This is a GPIO controller.

- #gpio-cells: Must be <2>.  The first cell is the GPIO pin.

- interrupt-controller: The GPIO controller is also an interrupt

  controller, many of its pins may be configured as an interrupt

  source.

- #interrupt-cells: Must be <2>.  The first cell is the GPIO pin

   connected to the interrupt source.  The second cell is the interrupt

   triggering protocol and may have one of four values:

   1 - edge triggered on the rising edge.

   2 - edge triggered on the falling edge

   4 - level triggered active high.

   8 - level triggered active low.

- interrupts: Interrupt routing for each pin.

Example:

	gpio-controller@1070000000800 {

		#gpio-cells = <2>;

		compatible = "cavium,octeon-3860-gpio";

		reg = <0x10700 0x00000800 0x0 0x100>;

		gpio-controller;

		/* Interrupts are specified by two parts:

		 * 1) GPIO pin number (0..15)

		 * 2) Triggering (1 - edge rising

		 *		  2 - edge falling

		 *		  4 - level active high

		 *		  8 - level active low)

		 */

		interrupt-controller;

		#interrupt-cells = <2>;

		/* The GPIO pin connect to 16 consecutive CUI bits */

		interrupts = <0 16>, <0 17>, <0 18>, <0 19>,

			     <0 20>, <0 21>, <0 22>, <0 23>,

			     <0 24>, <0 25>, <0 26>, <0 27>,

			     <0 28>, <0 29>, <0 30>, <0 31>;

	};

* Two Wire Serial Interface (TWSI) / I2C

- compatible: "cavium,octeon-3860-twsi"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the TWSI/I2C bus controller register bank.

- #address-cells: Must be <1>.

- #size-cells: Must be <0>.  I2C addresses have no size component.

- interrupts: A single interrupt specifier.

- clock-frequency: The I2C bus clock rate in Hz.

Example:

	twsi0: i2c@1180000001000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "cavium,octeon-3860-twsi";

		reg = <0x11800 0x00001000 0x0 0x200>;

		interrupts = <0 45>;

		clock-frequency = <100000>;

		rtc@68 {

			compatible = "dallas,ds1337";

			reg = <0x68>;

		};

		tmp@4c {

			compatible = "ti,tmp421";

			reg = <0x4c>;

		};

	};

* Boot Bus

The Octeon Boot Bus is a configurable parallel bus with 8 chip

selects.  Each chip select is independently configurable.

Properties:

- compatible: "cavium,octeon-3860-bootbus"

  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

- reg: The base address of the Boot Bus' register bank.

- #address-cells: Must be <2>.  The first cell is the chip select

   within the bootbus.  The second cell is the offset from the chip select.

- #size-cells: Must be <1>.

- ranges: There must be one one triplet of (child-bus-address,

  parent-bus-address, length) for each active chip select.  If the

  length element for any triplet is zero, the chip select is disabled,

  making it inactive.

The configuration parameters for each chip select are stored in child

nodes.

Configuration Properties:

- compatible:  "cavium,octeon-3860-bootbus-config"

- cavium,cs-index: A single cell indicating the chip select that

  corresponds to this configuration.

- cavium,t-adr: A cell specifying the ADR timing (in nS).

- cavium,t-ce: A cell specifying the CE timing (in nS).

- cavium,t-oe: A cell specifying the OE timing (in nS).

- cavium,t-we: A cell specifying the WE timing (in nS).

- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).

- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).

- cavium,t-pause: A cell specifying the PAUSE timing (in nS).

- cavium,t-wait: A cell specifying the WAIT timing (in nS).

- cavium,t-page: A cell specifying the PAGE timing (in nS).

- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).

- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1

  = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).

- cavium,wait-mode: Optional.  If present, wait mode (WAITM) is selected.

- cavium,page-mode: Optional.  If present, page mode (PAGEM) is selected.

- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of

  the bus for this chip select.

- cavium,ale-mode: Optional.  If present, ALE mode is selected.

- cavium,sam-mode: Optional.  If present, SAM mode is selected.

- cavium,or-mode: Optional.  If present, OR mode is selected.

Example:

	bootbus: bootbus@1180000000000 {

		compatible = "cavium,octeon-3860-bootbus";

		reg = <0x11800 0x00000000 0x0 0x200>;

		/* The chip select number and offset */

		#address-cells = <2>;

		/* The size of the chip select region */

		#size-cells = <1>;

		ranges = <0 0  0x0 0x1f400000  0xc00000>,

			 <1 0  0x10000 0x30000000  0>,

			 <2 0  0x10000 0x40000000  0>,

			 <3 0  0x10000 0x50000000  0>,

			 <4 0  0x0 0x1d020000  0x10000>,

			 <5 0  0x0 0x1d040000  0x10000>,

			 <6 0  0x0 0x1d050000  0x10000>,

			 <7 0  0x10000 0x90000000  0>;

			cavium,cs-config@0 {

			compatible = "cavium,octeon-3860-bootbus-config";

			cavium,cs-index = <0>;

			cavium,t-adr  = <20>;

			cavium,t-ce   = <60>;

			cavium,t-oe   = <60>;

			cavium,t-we   = <45>;

			cavium,t-rd-hld = <35>;

			cavium,t-wr-hld = <45>;

			cavium,t-pause  = <0>;

			cavium,t-wait   = <0>;

			cavium,t-page   = <35>;

			cavium,t-rd-dly = <0>;

			cavium,pages     = <0>;

			cavium,bus-width = <8>;

		};

		.

		.

		.

		cavium,cs-config@6 {

			compatible = "cavium,octeon-3860-bootbus-config";

			cavium,cs-index = <6>;

			cavium,t-adr  = <5>;

			cavium,t-ce   = <300>;

			cavium,t-oe   = <270>;

			cavium,t-we   = <150>;

			cavium,t-rd-hld = <100>;

			cavium,t-wr-hld = <70>;

			cavium,t-pause  = <0>;

			cavium,t-wait   = <0>;

			cavium,t-page   = <320>;

			cavium,t-rd-dly = <0>;

			cavium,pages     = <0>;

			cavium,wait-mode;

			cavium,bus-width = <16>;

		};

		.

		.

		.

	};

* Central Interrupt Unit

Properties:

- compatible: "cavium,octeon-3860-ciu"

  Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.

- interrupt-controller:  This is an interrupt controller.

- reg: The base address of the CIU's register bank.

- #interrupt-cells: Must be <2>.  The first cell is the bank within

   the CIU and may have a value of 0 or 1.  The second cell is the bit

   within the bank and may have a value between 0 and 63.

Example:

	interrupt-controller@1070000000000 {

		compatible = "cavium,octeon-3860-ciu";

		interrupt-controller;

		/* Interrupts are specified by two parts:

		 * 1) Controller register (0 or 1)

		 * 2) Bit within the register (0..63)

		 */

		#interrupt-cells = <2>;

		reg = <0x10700 0x00000000 0x0 0x7000>;

	};