Loading arch/arm64/boot/dts/qcom/sdm670-sde-display.dtsi +20 −4 Original line number Diff line number Diff line Loading @@ -137,9 +137,16 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk"; <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk", "src_byte_clk", "src_pixel_clk", "shadow_byte_clk", "shadow_pixel_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; Loading Loading @@ -209,8 +216,14 @@ qcom,dsi-ctrl = <&mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy1>; clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk"; <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll PCLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk", "src_byte_clk", "src_pixel_clk", "shadow_byte_clk", "shadow_pixel_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; Loading Loading @@ -632,6 +645,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <804948480 798240576 801594528 808302432 811656384>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 Loading arch/arm64/boot/dts/qcom/sdm670-sde-pll.dtsi +10 −5 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -18,11 +18,14 @@ #clock-cells = <1>; reg = <0xae94a00 0x1e0>, <0xae94400 0x800>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "gdsc_base"; <0xaf03000 0x8>, <0xae94200 0x100>; reg-names = "pll_base", "phy_base", "gdsc_base", "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; memory-region = <&dfps_data_memory>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; Loading @@ -45,8 +48,10 @@ #clock-cells = <1>; reg = <0xae96a00 0x1e0>, <0xae96400 0x800>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "gdsc_base"; <0xaf03000 0x8>, <0xae96200 0x100>; reg-names = "pll_base", "phy_base", "gdsc_base", "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; Loading arch/arm64/boot/dts/qcom/sdm670-sde.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -485,8 +485,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-0"; cell-index = <0>; reg = <0xae94400 0x7c0>; reg-names = "dsi_phy"; reg = <0xae94400 0x7c0>, <0xae94200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; gdsc-supply = <&mdss_core_gdsc>; vdda-0p9-supply = <&pm660l_l1>; qcom,platform-strength-ctrl = [55 03 Loading Loading @@ -518,8 +519,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-1"; cell-index = <1>; reg = <0xae96400 0x7c0>; reg-names = "dsi_phy"; reg = <0xae96400 0x7c0>, <0xae96200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; gdsc-supply = <&mdss_core_gdsc>; vdda-0p9-supply = <&pm660l_l1>; qcom,platform-strength-ctrl = [55 03 Loading arch/arm64/boot/dts/qcom/sdm670.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -596,10 +596,15 @@ }; cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; reg = <0x0 0x9c000000 0x0 0x2300000>; label = "cont_splash_region"; }; dfps_data_memory: dfps_data_region@9e300000 { reg = <0x0 0x9e300000 0x0 0x0100000>; label = "dfps_data_region"; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; Loading Loading
arch/arm64/boot/dts/qcom/sdm670-sde-display.dtsi +20 −4 Original line number Diff line number Diff line Loading @@ -137,9 +137,16 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, <&mdss_dsi0_pll PCLK_MUX_0_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk"; <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll PCLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk", "src_byte_clk", "src_pixel_clk", "shadow_byte_clk", "shadow_pixel_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; Loading Loading @@ -209,8 +216,14 @@ qcom,dsi-ctrl = <&mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy1>; clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk"; <&mdss_dsi1_pll PCLK_MUX_1_CLK>, <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll PCLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; clock-names = "mux_byte_clk", "mux_pixel_clk", "src_byte_clk", "src_pixel_clk", "shadow_byte_clk", "shadow_pixel_clk"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; Loading Loading @@ -632,6 +645,9 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-dyn-clk-enable; qcom,dsi-dyn-clk-list = <804948480 798240576 801594528 808302432 811656384>; qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 Loading
arch/arm64/boot/dts/qcom/sdm670-sde-pll.dtsi +10 −5 Original line number Diff line number Diff line /* Copyright (c) 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading @@ -18,11 +18,14 @@ #clock-cells = <1>; reg = <0xae94a00 0x1e0>, <0xae94400 0x800>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "gdsc_base"; <0xaf03000 0x8>, <0xae94200 0x100>; reg-names = "pll_base", "phy_base", "gdsc_base", "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; memory-region = <&dfps_data_memory>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; Loading @@ -45,8 +48,10 @@ #clock-cells = <1>; reg = <0xae96a00 0x1e0>, <0xae96400 0x800>, <0xaf03000 0x8>; reg-names = "pll_base", "phy_base", "gdsc_base"; <0xaf03000 0x8>, <0xae96200 0x100>; reg-names = "pll_base", "phy_base", "gdsc_base", "dynamic_pll_base"; clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; Loading
arch/arm64/boot/dts/qcom/sdm670-sde.dtsi +6 −4 Original line number Diff line number Diff line Loading @@ -485,8 +485,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-0"; cell-index = <0>; reg = <0xae94400 0x7c0>; reg-names = "dsi_phy"; reg = <0xae94400 0x7c0>, <0xae94200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; gdsc-supply = <&mdss_core_gdsc>; vdda-0p9-supply = <&pm660l_l1>; qcom,platform-strength-ctrl = [55 03 Loading Loading @@ -518,8 +519,9 @@ compatible = "qcom,dsi-phy-v3.0"; label = "dsi-phy-1"; cell-index = <1>; reg = <0xae96400 0x7c0>; reg-names = "dsi_phy"; reg = <0xae96400 0x7c0>, <0xae96200 0x100>; reg-names = "dsi_phy", "dyn_refresh_base"; gdsc-supply = <&mdss_core_gdsc>; vdda-0p9-supply = <&pm660l_l1>; qcom,platform-strength-ctrl = [55 03 Loading
arch/arm64/boot/dts/qcom/sdm670.dtsi +6 −1 Original line number Diff line number Diff line Loading @@ -596,10 +596,15 @@ }; cont_splash_memory: cont_splash_region@9c000000 { reg = <0x0 0x9c000000 0x0 0x02400000>; reg = <0x0 0x9c000000 0x0 0x2300000>; label = "cont_splash_region"; }; dfps_data_memory: dfps_data_region@9e300000 { reg = <0x0 0x9e300000 0x0 0x0100000>; label = "dfps_data_region"; }; dump_mem: mem_dump_region { compatible = "shared-dma-pool"; reusable; Loading