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Commit 68aa00ac authored by Cyrill Gorcunov's avatar Cyrill Gorcunov Committed by Ingo Molnar
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perf, x86: Make a second write to performance counter if needed 



On Netburst PMU we need a second write to a performance counter
due to cpu erratum.

A simple flag test instead of alternative instructions was choosen
because wrmsrl is already a macro and if virtualization is turned
on will need an additional wrapper call which is more expencise.

nb: we should propably switch to jump-labels as only this facility
reach the mainline.

Signed-off-by: default avatarCyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100602212304.GC5264@lenovo>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 8d2cacbb

arch/x86/kernel/cpu/perf_event.c

+11 −1
Original line number Diff line number Diff line
@@ -220,6 +220,7 @@ struct x86_pmu { 
						 struct perf_event *event);

	struct event_constraint *event_constraints;

	void		(*quirks)(void);

	int		perfctr_second_write;



	int		(*cpu_prepare)(int cpu);

	void		(*cpu_starting)(int cpu);
@@ -925,8 +926,17 @@ x86_perf_event_set_period(struct perf_event *event) 
	 */

	atomic64_set(&hwc->prev_count, (u64)-left);



	wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);



	/*

	 * Due to erratum on certan cpu we need

	 * a second write to be sure the register

	 * is updated properly

	 */

	if (x86_pmu.perfctr_second_write) {

		wrmsrl(hwc->event_base + idx,

			(u64)(-left) & x86_pmu.cntval_mask);

	}



	perf_event_update_userpage(event);

arch/x86/kernel/cpu/perf_event_p4.c

+9 −0
Original line number Diff line number Diff line
@@ -829,6 +829,15 @@ static __initconst const struct x86_pmu p4_pmu = { 
	.max_period		= (1ULL << 39) - 1,

	.hw_config		= p4_hw_config,

	.schedule_events	= p4_pmu_schedule_events,

	/*

	 * This handles erratum N15 in intel doc 249199-029,

	 * the counter may not be updated correctly on write

	 * so we need a second write operation to do the trick

	 * (the official workaround didn't work)

	 *

	 * the former idea is taken from OProfile code

	 */

	.perfctr_second_write	= 1,

};



static __init int p4_pmu_init(void)