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Commit 68892dee authored by Raviteja Tamatam's avatar Raviteja Tamatam Committed by Gerrit - the friendly Code Review server
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drm: msm: dsi-staging: add support for dfps 



Added support for dynamic fps change and to
enable/disable timing db during fps update along
with necessary logic to update fps. It also includes
updating the new fps mode in the connector probed list.

Change-Id: I10fd7f4388d1617b91251b06e67a8c05e1d2f54d
Signed-off-by: default avatarRaviteja Tamatam <travitej@codeaurora.org>
parent a45d8e7b

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, 
	ctrl->ops.video_engine_en        = dsi_ctrl_hw_cmn_video_engine_en;

	ctrl->ops.video_engine_setup     = dsi_ctrl_hw_cmn_video_engine_setup;

	ctrl->ops.set_video_timing       = dsi_ctrl_hw_cmn_set_video_timing;

	ctrl->ops.set_timing_db          = dsi_ctrl_hw_cmn_set_timing_db;

	ctrl->ops.cmd_engine_setup       = dsi_ctrl_hw_cmn_cmd_engine_setup;

	ctrl->ops.setup_cmd_stream       = dsi_ctrl_hw_cmn_setup_cmd_stream;

	ctrl->ops.ctrl_en                = dsi_ctrl_hw_cmn_ctrl_en;

drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h

+2 −1
Original line number Diff line number Diff line
@@ -132,7 +132,8 @@ void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl, 
				       struct dsi_video_engine_cfg *cfg);

void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,

			 struct dsi_mode_info *mode);



void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl,

				     bool enable);

void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,

				     struct dsi_host_common_cfg *common_cfg,

				     struct dsi_cmd_engine_cfg *cfg);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+49 −2
Original line number Diff line number Diff line
@@ -1645,7 +1645,7 @@ int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl, 


	host_mode = &dsi_ctrl->host_config.video_timing;

	memcpy(host_mode, timing, sizeof(*host_mode));



	dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, true);

	dsi_ctrl->hw.ops.set_video_timing(&dsi_ctrl->hw, host_mode);



exit:
@@ -1653,6 +1653,53 @@ int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl, 
	return rc;

}



/**

 * dsi_ctrl_timing_db_update() - update only controller Timing DB

 * @dsi_ctrl:          DSI controller handle.

 * @enable:            Enable/disable Timing DB register

 *

 *  Update timing db register value during dfps usecases

 *

 * Return: error code.

 */

int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl,

		bool enable)

{

	int rc = 0;



	if (!dsi_ctrl) {

		pr_err("Invalid dsi_ctrl\n");

		return -EINVAL;

	}



	mutex_lock(&dsi_ctrl->ctrl_lock);



	rc = dsi_ctrl_check_state(dsi_ctrl, DSI_CTRL_OP_ASYNC_TIMING,

			DSI_CTRL_ENGINE_ON);

	if (rc) {

		pr_err("[DSI_%d] Controller state check failed, rc=%d\n",

		       dsi_ctrl->cell_index, rc);

		goto exit;

	}



	/*

	 * Add HW recommended delay for dfps feature.

	 * When prefetch is enabled, MDSS HW works on 2 vsync

	 * boundaries i.e. mdp_vsync and panel_vsync.

	 * In the current implementation we are only waiting

	 * for mdp_vsync. We need to make sure that interface

	 * flush is after panel_vsync. So, added the recommended

	 * delays after dfps update.

	 */

	usleep_range(2000, 2010);



	dsi_ctrl->hw.ops.set_timing_db(&dsi_ctrl->hw, enable);



exit:

	mutex_unlock(&dsi_ctrl->ctrl_lock);

	return rc;

}



int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl)

{

	int rc = 0;
@@ -2146,7 +2193,7 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl, 
		goto error;

	}



	if (!(flags & DSI_MODE_FLAG_SEAMLESS)) {

	if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR))) {

		rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle);

		if (rc) {

			pr_err("[%s] failed to update link frequencies, rc=%d\n",

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+12 −0
Original line number Diff line number Diff line
@@ -310,6 +310,18 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *dsi_ctrl, 
				struct dsi_host_config *config,

				int flags, void *clk_handle);



/**

 * dsi_ctrl_timing_db_update() - update only controller Timing DB

 * @dsi_ctrl:          DSI controller handle.

 * @enable:            Enable/disable Timing DB register

 *

 * Update timing db register value during dfps usecases

 *

 * Return: error code.

 */

int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl,

		bool enable);



/**

 * dsi_ctrl_async_timing_update() - update only controller timing

 * @dsi_ctrl:          DSI controller handle.

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h

+9 −0
Original line number Diff line number Diff line
@@ -695,6 +695,15 @@ struct dsi_ctrl_hw_ops { 
	u32 (*collect_misr)(struct dsi_ctrl_hw *ctrl,

			    enum dsi_op_mode panel_mode);



	/**

	 * set_timing_db() - enable/disable Timing DB register

	 * @ctrl:          Pointer to controller host hardware.

	 * @enable:        Enable/Disable flag.

	 *

	 * Enable or Disabe the Timing DB register.

	 */

	void (*set_timing_db)(struct dsi_ctrl_hw *ctrl,

				 bool enable);

};



/*