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Commit 683595a6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add VCE 2.0 register headers 



These are register headers for the VCE (Video Codec Engine)
block on the GPU.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3b1e08cb

drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_d.h

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/*

 * VCE_2_0 Register documentation

 *

 * Copyright (C) 2014  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */



#ifndef VCE_2_0_D_H

#define VCE_2_0_D_H



#define mmVCE_STATUS                                                            0x8001

#define mmVCE_VCPU_CNTL                                                         0x8005

#define mmVCE_VCPU_CACHE_OFFSET0                                                0x8009

#define mmVCE_VCPU_CACHE_SIZE0                                                  0x800a

#define mmVCE_VCPU_CACHE_OFFSET1                                                0x800b

#define mmVCE_VCPU_CACHE_SIZE1                                                  0x800c

#define mmVCE_VCPU_CACHE_OFFSET2                                                0x800d

#define mmVCE_VCPU_CACHE_SIZE2                                                  0x800e

#define mmVCE_SOFT_RESET                                                        0x8048

#define mmVCE_RB_BASE_LO2                                                       0x805b

#define mmVCE_RB_BASE_HI2                                                       0x805c

#define mmVCE_RB_SIZE2                                                          0x805d

#define mmVCE_RB_RPTR2                                                          0x805e

#define mmVCE_RB_WPTR2                                                          0x805f

#define mmVCE_RB_BASE_LO                                                        0x8060

#define mmVCE_RB_BASE_HI                                                        0x8061

#define mmVCE_RB_SIZE                                                           0x8062

#define mmVCE_RB_RPTR                                                           0x8063

#define mmVCE_RB_WPTR                                                           0x8064

#define mmVCE_RB_ARB_CTRL                                                       0x809f

#define mmVCE_CLOCK_GATING_A                                                    0x80be

#define mmVCE_CLOCK_GATING_B                                                    0x80bf

#define mmVCE_UENC_DMA_DCLK_CTRL                                                0x8390

#define mmVCE_CGTT_CLK_OVERRIDE                                                 0x81e8

#define mmVCE_UENC_CLOCK_GATING                                                 0x81ef

#define mmVCE_UENC_REG_CLOCK_GATING                                             0x81f0

#define mmVCE_SYS_INT_EN                                                        0x84c0

#define mmVCE_SYS_INT_STATUS                                                    0x84c1

#define mmVCE_SYS_INT_ACK                                                       0x84c1

#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR                                          0x8517

#define mmVCE_LMI_CTRL2                                                         0x851d

#define mmVCE_LMI_SWAP_CNTL3                                                    0x851e

#define mmVCE_LMI_CTRL                                                          0x8526

#define mmVCE_LMI_STATUS                                                        0x8527

#define mmVCE_LMI_VM_CTRL                                                       0x8528

#define mmVCE_LMI_SWAP_CNTL                                                     0x852d

#define mmVCE_LMI_SWAP_CNTL1                                                    0x852e

#define mmVCE_LMI_SWAP_CNTL2                                                    0x8533

#define mmVCE_LMI_MISC_CTRL                                                     0x8535

#define mmVCE_LMI_CACHE_CTRL                                                    0x853d



#endif /* VCE_2_0_D_H */

drivers/gpu/drm/amd/include/asic_reg/vce/vce_2_0_sh_mask.h

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/*

 * VCE_2_0 Register documentation

 *

 * Copyright (C) 2014  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */



#ifndef VCE_2_0_SH_MASK_H

#define VCE_2_0_SH_MASK_H



#define VCE_STATUS__JOB_BUSY_MASK 0x1

#define VCE_STATUS__JOB_BUSY__SHIFT 0x0

#define VCE_STATUS__VCPU_REPORT_MASK 0xfe

#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1

#define VCE_STATUS__UENC_BUSY_MASK 0x100

#define VCE_STATUS__UENC_BUSY__SHIFT 0x8

#define VCE_VCPU_CNTL__CLK_EN_MASK 0x1

#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0

#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x40000

#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12

#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0xfffffff

#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0

#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0xffffff

#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0

#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0xfffffff

#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0

#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0xffffff

#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0

#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0xfffffff

#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0

#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0xffffff

#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0

#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1

#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0

#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xffffffc0

#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6

#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xffffffff

#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0

#define VCE_RB_SIZE2__RB_SIZE_MASK 0x7ffff0

#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4

#define VCE_RB_RPTR2__RB_RPTR_MASK 0x7ffff0

#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4

#define VCE_RB_WPTR2__RB_WPTR_MASK 0x7ffff0

#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4

#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xffffffc0

#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6

#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xffffffff

#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0

#define VCE_RB_SIZE__RB_SIZE_MASK 0x7ffff0

#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4

#define VCE_RB_RPTR__RB_RPTR_MASK 0x7ffff0

#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4

#define VCE_RB_WPTR__RB_WPTR_MASK 0x7ffff0

#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4

#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1

#define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT 0x0

#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK 0x2

#define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1

#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK 0x4

#define VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT 0x2

#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8

#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3

#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8

#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3

#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8

#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3

#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xffffffff

#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0

#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100

#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8

#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3

#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0

#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000

#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15

#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3

#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0

#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x3ffc

#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2

#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3

#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0

#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x3ffc

#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2

#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0xff

#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0

#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1

#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0



#endif /* VCE_2_0_SH_MASK_H */