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Commit 673dd36f authored by Mark A. Greer's avatar Mark A. Greer Committed by Kevin Hilman
Browse files

davinci: Move interrupt ctlr info to SoC infrastructure 



Use the SoC infrastructure to hold the interrupt controller
information (i.e., base address, default priorities,
interrupt controller type, and the number of IRQs).

The interrupt controller base, although initially put
in the soc_info structure's intc_base field, is eventually
put in the global 'davinci_intc_base' so the low-level
interrupt code can access it without a dereference.

These changes enable the SoC default irq priorities to be
put in the SoC-specific files, and the interrupt controller
to be at any base address.

Signed-off-by: default avatarMark A. Greer <mgreer@mvista.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
parent 0e585952

arch/arm/mach-davinci/common.c

+3 −0
Original line number Diff line number Diff line
@@ -22,6 +22,8 @@ 
struct davinci_soc_info davinci_soc_info;

EXPORT_SYMBOL(davinci_soc_info);



void __iomem *davinci_intc_base;



static struct davinci_id * __init davinci_get_id(u32 jtag_id)

{

	int i;
@@ -84,6 +86,7 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info) 
			goto err;

	}



	davinci_intc_base = davinci_soc_info.intc_base;

	return;



err:

arch/arm/mach-davinci/dm355.c

+69 −0
Original line number Diff line number Diff line
@@ -470,6 +470,71 @@ EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false) 
#endif

};



static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {

	[IRQ_DM355_CCDC_VDINT0]		= 2,

	[IRQ_DM355_CCDC_VDINT1]		= 6,

	[IRQ_DM355_CCDC_VDINT2]		= 6,

	[IRQ_DM355_IPIPE_HST]		= 6,

	[IRQ_DM355_H3AINT]		= 6,

	[IRQ_DM355_IPIPE_SDR]		= 6,

	[IRQ_DM355_IPIPEIFINT]		= 6,

	[IRQ_DM355_OSDINT]		= 7,

	[IRQ_DM355_VENCINT]		= 6,

	[IRQ_ASQINT]			= 6,

	[IRQ_IMXINT]			= 6,

	[IRQ_USBINT]			= 4,

	[IRQ_DM355_RTOINT]		= 4,

	[IRQ_DM355_UARTINT2]		= 7,

	[IRQ_DM355_TINT6]		= 7,

	[IRQ_CCINT0]			= 5,	/* dma */

	[IRQ_CCERRINT]			= 5,	/* dma */

	[IRQ_TCERRINT0]			= 5,	/* dma */

	[IRQ_TCERRINT]			= 5,	/* dma */

	[IRQ_DM355_SPINT2_1]		= 7,

	[IRQ_DM355_TINT7]		= 4,

	[IRQ_DM355_SDIOINT0]		= 7,

	[IRQ_MBXINT]			= 7,

	[IRQ_MBRINT]			= 7,

	[IRQ_MMCINT]			= 7,

	[IRQ_DM355_MMCINT1]		= 7,

	[IRQ_DM355_PWMINT3]		= 7,

	[IRQ_DDRINT]			= 7,

	[IRQ_AEMIFINT]			= 7,

	[IRQ_DM355_SDIOINT1]		= 4,

	[IRQ_TINT0_TINT12]		= 2,	/* clockevent */

	[IRQ_TINT0_TINT34]		= 2,	/* clocksource */

	[IRQ_TINT1_TINT12]		= 7,	/* DSP timer */

	[IRQ_TINT1_TINT34]		= 7,	/* system tick */

	[IRQ_PWMINT0]			= 7,

	[IRQ_PWMINT1]			= 7,

	[IRQ_PWMINT2]			= 7,

	[IRQ_I2C]			= 3,

	[IRQ_UARTINT0]			= 3,

	[IRQ_UARTINT1]			= 3,

	[IRQ_DM355_SPINT0_0]		= 3,

	[IRQ_DM355_SPINT0_1]		= 3,

	[IRQ_DM355_GPIO0]		= 3,

	[IRQ_DM355_GPIO1]		= 7,

	[IRQ_DM355_GPIO2]		= 4,

	[IRQ_DM355_GPIO3]		= 4,

	[IRQ_DM355_GPIO4]		= 7,

	[IRQ_DM355_GPIO5]		= 7,

	[IRQ_DM355_GPIO6]		= 7,

	[IRQ_DM355_GPIO7]		= 7,

	[IRQ_DM355_GPIO8]		= 7,

	[IRQ_DM355_GPIO9]		= 7,

	[IRQ_DM355_GPIOBNK0]		= 7,

	[IRQ_DM355_GPIOBNK1]		= 7,

	[IRQ_DM355_GPIOBNK2]		= 7,

	[IRQ_DM355_GPIOBNK3]		= 7,

	[IRQ_DM355_GPIOBNK4]		= 7,

	[IRQ_DM355_GPIOBNK5]		= 7,

	[IRQ_DM355_GPIOBNK6]		= 7,

	[IRQ_COMMTX]			= 7,

	[IRQ_COMMRX]			= 7,

	[IRQ_EMUINT]			= 7,

};



/*----------------------------------------------------------------------*/



static const s8 dma_chan_dm355_no_event[] = {
@@ -563,6 +628,10 @@ static struct davinci_soc_info davinci_soc_info_dm355 = { 
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),

	.pinmux_pins		= dm355_pins,

	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),

	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),

	.intc_type		= DAVINCI_INTC_TYPE_AINTC,

	.intc_irq_prios		= dm355_default_priorities,

	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,

};



void __init dm355_init(void)

arch/arm/mach-davinci/dm644x.c

+72 −0
Original line number Diff line number Diff line
@@ -390,6 +390,74 @@ MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false) 
#endif

};



/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */

static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {

	[IRQ_VDINT0]		= 2,

	[IRQ_VDINT1]		= 6,

	[IRQ_VDINT2]		= 6,

	[IRQ_HISTINT]		= 6,

	[IRQ_H3AINT]		= 6,

	[IRQ_PRVUINT]		= 6,

	[IRQ_RSZINT]		= 6,

	[7]			= 7,

	[IRQ_VENCINT]		= 6,

	[IRQ_ASQINT]		= 6,

	[IRQ_IMXINT]		= 6,

	[IRQ_VLCDINT]		= 6,

	[IRQ_USBINT]		= 4,

	[IRQ_EMACINT]		= 4,

	[14]			= 7,

	[15]			= 7,

	[IRQ_CCINT0]		= 5,	/* dma */

	[IRQ_CCERRINT]		= 5,	/* dma */

	[IRQ_TCERRINT0]		= 5,	/* dma */

	[IRQ_TCERRINT]		= 5,	/* dma */

	[IRQ_PSCIN]		= 7,

	[21]			= 7,

	[IRQ_IDE]		= 4,

	[23]			= 7,

	[IRQ_MBXINT]		= 7,

	[IRQ_MBRINT]		= 7,

	[IRQ_MMCINT]		= 7,

	[IRQ_SDIOINT]		= 7,

	[28]			= 7,

	[IRQ_DDRINT]		= 7,

	[IRQ_AEMIFINT]		= 7,

	[IRQ_VLQINT]		= 4,

	[IRQ_TINT0_TINT12]	= 2,	/* clockevent */

	[IRQ_TINT0_TINT34]	= 2,	/* clocksource */

	[IRQ_TINT1_TINT12]	= 7,	/* DSP timer */

	[IRQ_TINT1_TINT34]	= 7,	/* system tick */

	[IRQ_PWMINT0]		= 7,

	[IRQ_PWMINT1]		= 7,

	[IRQ_PWMINT2]		= 7,

	[IRQ_I2C]		= 3,

	[IRQ_UARTINT0]		= 3,

	[IRQ_UARTINT1]		= 3,

	[IRQ_UARTINT2]		= 3,

	[IRQ_SPINT0]		= 3,

	[IRQ_SPINT1]		= 3,

	[45]			= 7,

	[IRQ_DSP2ARM0]		= 4,

	[IRQ_DSP2ARM1]		= 4,

	[IRQ_GPIO0]		= 7,

	[IRQ_GPIO1]		= 7,

	[IRQ_GPIO2]		= 7,

	[IRQ_GPIO3]		= 7,

	[IRQ_GPIO4]		= 7,

	[IRQ_GPIO5]		= 7,

	[IRQ_GPIO6]		= 7,

	[IRQ_GPIO7]		= 7,

	[IRQ_GPIOBNK0]		= 7,

	[IRQ_GPIOBNK1]		= 7,

	[IRQ_GPIOBNK2]		= 7,

	[IRQ_GPIOBNK3]		= 7,

	[IRQ_GPIOBNK4]		= 7,

	[IRQ_COMMTX]		= 7,

	[IRQ_COMMRX]		= 7,

	[IRQ_EMUINT]		= 7,

};



/*----------------------------------------------------------------------*/



static const s8 dma_chan_dm644x_no_event[] = {
@@ -503,6 +571,10 @@ static struct davinci_soc_info davinci_soc_info_dm644x = { 
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),

	.pinmux_pins		= dm644x_pins,

	.pinmux_pins_num	= ARRAY_SIZE(dm644x_pins),

	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),

	.intc_type		= DAVINCI_INTC_TYPE_AINTC,

	.intc_irq_prios 	= dm644x_default_priorities,

	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,

};



void __init dm644x_init(void)

arch/arm/mach-davinci/dm646x.c

+71 −0
Original line number Diff line number Diff line
@@ -358,6 +358,73 @@ MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) 
#endif

};



static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {

	[IRQ_DM646X_VP_VERTINT0]        = 7,

	[IRQ_DM646X_VP_VERTINT1]        = 7,

	[IRQ_DM646X_VP_VERTINT2]        = 7,

	[IRQ_DM646X_VP_VERTINT3]        = 7,

	[IRQ_DM646X_VP_ERRINT]          = 7,

	[IRQ_DM646X_RESERVED_1]         = 7,

	[IRQ_DM646X_RESERVED_2]         = 7,

	[IRQ_DM646X_WDINT]              = 7,

	[IRQ_DM646X_CRGENINT0]          = 7,

	[IRQ_DM646X_CRGENINT1]          = 7,

	[IRQ_DM646X_TSIFINT0]           = 7,

	[IRQ_DM646X_TSIFINT1]           = 7,

	[IRQ_DM646X_VDCEINT]            = 7,

	[IRQ_DM646X_USBINT]             = 7,

	[IRQ_DM646X_USBDMAINT]          = 7,

	[IRQ_DM646X_PCIINT]             = 7,

	[IRQ_CCINT0]                    = 7,    /* dma */

	[IRQ_CCERRINT]                  = 7,    /* dma */

	[IRQ_TCERRINT0]                 = 7,    /* dma */

	[IRQ_TCERRINT]                  = 7,    /* dma */

	[IRQ_DM646X_TCERRINT2]          = 7,

	[IRQ_DM646X_TCERRINT3]          = 7,

	[IRQ_DM646X_IDE]                = 7,

	[IRQ_DM646X_HPIINT]             = 7,

	[IRQ_DM646X_EMACRXTHINT]        = 7,

	[IRQ_DM646X_EMACRXINT]          = 7,

	[IRQ_DM646X_EMACTXINT]          = 7,

	[IRQ_DM646X_EMACMISCINT]        = 7,

	[IRQ_DM646X_MCASP0TXINT]        = 7,

	[IRQ_DM646X_MCASP0RXINT]        = 7,

	[IRQ_AEMIFINT]                  = 7,

	[IRQ_DM646X_RESERVED_3]         = 7,

	[IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */

	[IRQ_TINT0_TINT34]              = 7,    /* clocksource */

	[IRQ_TINT1_TINT12]              = 7,    /* DSP timer */

	[IRQ_TINT1_TINT34]              = 7,    /* system tick */

	[IRQ_PWMINT0]                   = 7,

	[IRQ_PWMINT1]                   = 7,

	[IRQ_DM646X_VLQINT]             = 7,

	[IRQ_I2C]                       = 7,

	[IRQ_UARTINT0]                  = 7,

	[IRQ_UARTINT1]                  = 7,

	[IRQ_DM646X_UARTINT2]           = 7,

	[IRQ_DM646X_SPINT0]             = 7,

	[IRQ_DM646X_SPINT1]             = 7,

	[IRQ_DM646X_DSP2ARMINT]         = 7,

	[IRQ_DM646X_RESERVED_4]         = 7,

	[IRQ_DM646X_PSCINT]             = 7,

	[IRQ_DM646X_GPIO0]              = 7,

	[IRQ_DM646X_GPIO1]              = 7,

	[IRQ_DM646X_GPIO2]              = 7,

	[IRQ_DM646X_GPIO3]              = 7,

	[IRQ_DM646X_GPIO4]              = 7,

	[IRQ_DM646X_GPIO5]              = 7,

	[IRQ_DM646X_GPIO6]              = 7,

	[IRQ_DM646X_GPIO7]              = 7,

	[IRQ_DM646X_GPIOBNK0]           = 7,

	[IRQ_DM646X_GPIOBNK1]           = 7,

	[IRQ_DM646X_GPIOBNK2]           = 7,

	[IRQ_DM646X_DDRINT]             = 7,

	[IRQ_DM646X_AEMIFINT]           = 7,

	[IRQ_COMMTX]                    = 7,

	[IRQ_COMMRX]                    = 7,

	[IRQ_EMUINT]                    = 7,

};



/*----------------------------------------------------------------------*/



static const s8 dma_chan_dm646x_no_event[] = {
@@ -483,6 +550,10 @@ static struct davinci_soc_info davinci_soc_info_dm646x = { 
	.pinmux_base		= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),

	.pinmux_pins		= dm646x_pins,

	.pinmux_pins_num	= ARRAY_SIZE(dm646x_pins),

	.intc_base		= IO_ADDRESS(DAVINCI_ARM_INTC_BASE),

	.intc_type		= DAVINCI_INTC_TYPE_AINTC,

	.intc_irq_prios		= dm646x_default_priorities,

	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,

};



void __init dm646x_init(void)

arch/arm/mach-davinci/include/mach/common.h

+5 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ struct sys_timer; 
extern struct sys_timer davinci_timer;



extern void davinci_irq_init(void);

extern void __iomem *davinci_intc_base;



/* parameters describe VBUS sourcing for host mode */

extern void setup_usb(unsigned mA, unsigned potpgt_msec);
@@ -39,6 +40,10 @@ struct davinci_soc_info { 
	void __iomem			*pinmux_base;

	const struct mux_config		*pinmux_pins;

	unsigned long			pinmux_pins_num;

	void __iomem			*intc_base;

	int				intc_type;

	u8				*intc_irq_prios;

	unsigned long			intc_irq_num;

};



extern struct davinci_soc_info davinci_soc_info;