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Commit 66e514c1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2014-03-21' of git://anongit.freedesktop.org/drm-intel into drm-next 

- Inherit/reuse firmwar framebuffers (for real this time) from Jesse, less
  flicker for fastbooting.
- More flexible cloning for hdmi (Ville).
- Some PPGTT fixes from Ben.
- Ring init fixes from Naresh Kumar.
- set_cache_level regression fixes for the vma conversion from Ville&Chris.
- Conversion to the new dp aux helpers (Jani).
- Unification of runtime pm with pc8 support from Paulo, prep work for runtime
  pm on other platforms than HSW.
- Larger cursor sizes (Sagar Kamble).
- Piles of improvements and fixes all over, as usual.

* tag 'drm-intel-next-2014-03-21' of git://anongit.freedesktop.org/drm-intel: (75 commits)
  drm/i915: Include a note about the dangers of I915_READ64/I915_WRITE64
  drm/i915/sdvo: fix questionable return value check
  drm/i915: Fix unsafe loop iteration over vma whilst unbinding them
  drm/i915: Enabling 128x128 and 256x256 ARGB Cursor Support
  drm/i915: Print how many objects are shared in per-process stats
  drm/i915: Per-process stats work better when evaluated per-process
  drm/i915: remove rps local variables
  drm/i915: Remove extraneous MMIO for RPS
  drm/i915: Rename and comment all the RPS *stuff*
  drm/i915: Store the HW min frequency as min_freq
  drm/i915: Fix coding style for RPS
  drm/i915: Reorganize the overclock code
  drm/i915: init pm.suspended earlier
  drm/i915: update the PC8 and runtime PM documentation
  drm/i915: rename __hsw_do_{en, dis}able_pc8
  drm/i915: kill struct i915_package_c8
  drm/i915: move pc8.irqs_disabled to pm.irqs_disabled
  drm/i915: remove dev_priv->pc8.enabled
  drm/i915: don't get/put PC8 when getting/putting power wells
  drm/i915: make intel_aux_display_runtime_get get runtime PM, not PC8
  ...

Conflicts:
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i915/intel_dp.c
parents 2844ea3f 698b3135

drivers/gpu/drm/drm_dp_helper.c

+2 −1
Original line number Diff line number Diff line
@@ -726,7 +726,8 @@ int drm_dp_aux_register_i2c_bus(struct drm_dp_aux *aux) 
	aux->ddc.dev.parent = aux->dev;

	aux->ddc.dev.of_node = aux->dev->of_node;



	strncpy(aux->ddc.name, dev_name(aux->dev), sizeof(aux->ddc.name));

	strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),

		sizeof(aux->ddc.name));



	return i2c_add_adapter(&aux->ddc);

}

drivers/gpu/drm/i915/i915_cmd_parser.c

+1 −1
Original line number Diff line number Diff line
@@ -402,7 +402,7 @@ int i915_parse_cmds(struct intel_ring_buffer *ring, 
			length = ((*cmd & desc->length.mask) + LENGTH_BIAS);



		if ((batch_end - cmd) < length) {

			DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%ld\n",

			DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n",

					 *cmd,

					 length,

					 (unsigned long)(batch_end - cmd));

drivers/gpu/drm/i915/i915_debugfs.c

+110 −38
Original line number Diff line number Diff line
@@ -299,27 +299,61 @@ static int i915_gem_stolen_list_info(struct seq_file *m, void *data) 
} while (0)



struct file_stats {

	struct drm_i915_file_private *file_priv;

	int count;

	size_t total, active, inactive, unbound;

	size_t total, unbound;

	size_t global, shared;

	size_t active, inactive;

};



static int per_file_stats(int id, void *ptr, void *data)

{

	struct drm_i915_gem_object *obj = ptr;

	struct file_stats *stats = data;

	struct i915_vma *vma;



	stats->count++;

	stats->total += obj->base.size;



	if (i915_gem_obj_ggtt_bound(obj)) {

		if (!list_empty(&obj->ring_list))

	if (obj->base.name || obj->base.dma_buf)

		stats->shared += obj->base.size;



	if (USES_FULL_PPGTT(obj->base.dev)) {

		list_for_each_entry(vma, &obj->vma_list, vma_link) {

			struct i915_hw_ppgtt *ppgtt;



			if (!drm_mm_node_allocated(&vma->node))

				continue;



			if (i915_is_ggtt(vma->vm)) {

				stats->global += obj->base.size;

				continue;

			}



			ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);

			if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)

				continue;



			if (obj->ring) /* XXX per-vma statistic */

				stats->active += obj->base.size;

			else

				stats->inactive += obj->base.size;



			return 0;

		}

	} else {

		if (i915_gem_obj_ggtt_bound(obj)) {

			stats->global += obj->base.size;

			if (obj->ring)

				stats->active += obj->base.size;

			else

				stats->inactive += obj->base.size;

			return 0;

		}

	}



	if (!list_empty(&obj->global_list))

		stats->unbound += obj->base.size;

	}



	return 0;

}
@@ -411,6 +445,7 @@ static int i915_gem_object_info(struct seq_file *m, void* data) 
		struct task_struct *task;



		memset(&stats, 0, sizeof(stats));

		stats.file_priv = file->driver_priv;

		idr_for_each(&file->object_idr, per_file_stats, &stats);

		/*

		 * Although we have a valid reference on file->pid, that does
@@ -420,12 +455,14 @@ static int i915_gem_object_info(struct seq_file *m, void* data) 
		 */

		rcu_read_lock();

		task = pid_task(file->pid, PIDTYPE_PID);

		seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",

		seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",

			   task ? task->comm : "<unknown>",

			   stats.count,

			   stats.total,

			   stats.active,

			   stats.inactive,

			   stats.global,

			   stats.shared,

			   stats.unbound);

		rcu_read_unlock();

	}
@@ -1026,7 +1063,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
			   max_freq * GT_FREQUENCY_MULTIPLIER);



		seq_printf(m, "Max overclocked frequency: %dMHz\n",

			   dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);

			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);

	} else if (IS_VALLEYVIEW(dev)) {

		u32 freq_sts, val;
@@ -1498,8 +1535,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 


	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");



	for (gpu_freq = dev_priv->rps.min_delay;

	     gpu_freq <= dev_priv->rps.max_delay;

	for (gpu_freq = dev_priv->rps.min_freq_softlimit;

	     gpu_freq <= dev_priv->rps.max_freq_softlimit;

	     gpu_freq++) {

		ia_freq = gpu_freq;

		sandybridge_pcode_read(dev_priv,
@@ -2012,15 +2049,9 @@ static int i915_pc8_status(struct seq_file *m, void *unused) 
		return 0;

	}



	mutex_lock(&dev_priv->pc8.lock);

	seq_printf(m, "Requirements met: %s\n",

		   yesno(dev_priv->pc8.requirements_met));

	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));

	seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);

	seq_printf(m, "IRQs disabled: %s\n",

		   yesno(dev_priv->pc8.irqs_disabled));

	seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));

	mutex_unlock(&dev_priv->pc8.lock);

		   yesno(dev_priv->pm.irqs_disabled));



	return 0;

}
@@ -2248,24 +2279,67 @@ static void intel_connector_info(struct seq_file *m, 
		intel_seq_print_mode(m, 2, mode);

}



static bool cursor_active(struct drm_device *dev, int pipe)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 state;



	if (IS_845G(dev) || IS_I865G(dev))

		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;

	else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))

		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;

	else

		state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;



	return state;

}



static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 pos;



	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))

		pos = I915_READ(CURPOS_IVB(pipe));

	else

		pos = I915_READ(CURPOS(pipe));



	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;

	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))

		*x = -*x;



	*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;

	if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))

		*y = -*y;



	return cursor_active(dev, pipe);

}



static int i915_display_info(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_crtc *crtc;

	struct intel_crtc *crtc;

	struct drm_connector *connector;



	drm_modeset_lock_all(dev);

	seq_printf(m, "CRTC info\n");

	seq_printf(m, "---------\n");

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {

		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {

		bool active;

		int x, y;



		seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",

			   crtc->base.id, pipe_name(intel_crtc->pipe),

			   intel_crtc->active ? "yes" : "no");

		if (intel_crtc->active)

			intel_crtc_info(m, intel_crtc);

			   crtc->base.base.id, pipe_name(crtc->pipe),

			   yesno(crtc->active));

		if (crtc->active)

			intel_crtc_info(m, crtc);



		active = cursor_position(dev, crtc->pipe, &x, &y);

		seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",

			   yesno(crtc->cursor_visible),

			   x, y, crtc->cursor_addr,

			   yesno(active));

	}



	seq_printf(m, "\n");
@@ -2603,8 +2677,6 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 
	if (need_stable_symbols) {

		uint32_t tmp = I915_READ(PORT_DFT2_G4X);



		WARN_ON(!IS_G4X(dev));



		tmp |= DC_BALANCE_RESET_VLV;

		if (pipe == PIPE_A)

			tmp |= PIPE_A_SCRAMBLE_RESET;
@@ -3414,9 +3486,9 @@ i915_max_freq_get(void *data, u64 *val) 
		return ret;



	if (IS_VALLEYVIEW(dev))

		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);

		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);

	else

		*val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;

		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);



	return 0;
@@ -3453,16 +3525,16 @@ i915_max_freq_set(void *data, u64 val) 
		do_div(val, GT_FREQUENCY_MULTIPLIER);



		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

		hw_max = dev_priv->rps.hw_max;

		hw_max = dev_priv->rps.max_freq;

		hw_min = (rp_state_cap >> 16) & 0xff;

	}



	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {

	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {

		mutex_unlock(&dev_priv->rps.hw_lock);

		return -EINVAL;

	}



	dev_priv->rps.max_delay = val;

	dev_priv->rps.max_freq_softlimit = val;



	if (IS_VALLEYVIEW(dev))

		valleyview_set_rps(dev, val);
@@ -3495,9 +3567,9 @@ i915_min_freq_get(void *data, u64 *val) 
		return ret;



	if (IS_VALLEYVIEW(dev))

		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);

		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);

	else

		*val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;

		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;

	mutex_unlock(&dev_priv->rps.hw_lock);



	return 0;
@@ -3534,16 +3606,16 @@ i915_min_freq_set(void *data, u64 val) 
		do_div(val, GT_FREQUENCY_MULTIPLIER);



		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

		hw_max = dev_priv->rps.hw_max;

		hw_max = dev_priv->rps.max_freq;

		hw_min = (rp_state_cap >> 16) & 0xff;

	}



	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {

	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {

		mutex_unlock(&dev_priv->rps.hw_lock);

		return -EINVAL;

	}



	dev_priv->rps.min_delay = val;

	dev_priv->rps.min_freq_softlimit = val;



	if (IS_VALLEYVIEW(dev))

		valleyview_set_rps(dev, val);

drivers/gpu/drm/i915/i915_dma.c

+3 −4
Original line number Diff line number Diff line
@@ -1187,6 +1187,9 @@ intel_setup_mchbar(struct drm_device *dev) 
	u32 temp;

	bool enabled;



	if (IS_VALLEYVIEW(dev))

		return;



	dev_priv->mchbar_need_disable = false;



	if (IS_I915G(dev) || IS_I915GM(dev)) {
@@ -1608,8 +1611,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		goto put_bridge;

	}



	intel_uncore_early_sanitize(dev);



	/* This must be called before any calls to HAS_PCH_* */

	intel_detect_pch(dev);
@@ -1822,8 +1823,6 @@ int i915_driver_unload(struct drm_device *dev) 
	cancel_work_sync(&dev_priv->gpu_error.work);

	i915_destroy_error_state(dev);



	cancel_delayed_work_sync(&dev_priv->pc8.enable_work);



	if (dev->pdev->msi_enabled)

		pci_disable_msi(dev->pdev);

drivers/gpu/drm/i915/i915_drv.c

+9 −5
Original line number Diff line number Diff line
@@ -428,7 +428,6 @@ static int i915_drm_freeze(struct drm_device *dev) 


	/* We do a lot of poking in a lot of registers, make sure they work

	 * properly. */

	hsw_disable_package_c8(dev_priv);

	intel_display_set_init_power(dev_priv, true);



	drm_kms_helper_poll_disable(dev);
@@ -467,6 +466,7 @@ static int i915_drm_freeze(struct drm_device *dev) 
	i915_save_state(dev);



	intel_opregion_fini(dev);

	intel_uncore_fini(dev);



	console_lock();

	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
@@ -603,10 +603,6 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
		schedule_work(&dev_priv->console_resume_work);

	}



	/* Undo what we did at i915_drm_freeze so the refcount goes back to the

	 * expected level. */

	hsw_enable_package_c8(dev_priv);



	mutex_lock(&dev_priv->modeset_restore_lock);

	dev_priv->modeset_restore = MODESET_DONE;

	mutex_unlock(&dev_priv->modeset_restore_lock);
@@ -848,6 +844,9 @@ static int i915_runtime_suspend(struct device *device) 


	DRM_DEBUG_KMS("Suspending device\n");



	if (HAS_PC8(dev))

		hsw_enable_pc8(dev_priv);



	i915_gem_release_all_mmaps(dev_priv);



	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
@@ -862,6 +861,7 @@ static int i915_runtime_suspend(struct device *device) 
	 */

	intel_opregion_notify_adapter(dev, PCI_D1);



	DRM_DEBUG_KMS("Device suspended\n");

	return 0;

}
@@ -878,6 +878,10 @@ static int i915_runtime_resume(struct device *device) 
	intel_opregion_notify_adapter(dev, PCI_D0);

	dev_priv->pm.suspended = false;



	if (HAS_PC8(dev))

		hsw_disable_pc8(dev_priv);



	DRM_DEBUG_KMS("Device resumed\n");

	return 0;

}