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Commit 66c826a1 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915/vlv: fix RC6 residency time calculation 



The divider value to convert from CZ clock rate to ms needs a +1
adjustment on VLV just like on CHV. This matches both the spec and
the accuracy test by pm_rc6_residency.

v2:
- simplify logic checking for the CHV 320MHz special case (Rodrigo)

Testcase: igt/pm_rc6_residency
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76877


Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3320e37f

drivers/gpu/drm/i915/i915_sysfs.c

+7 −15
Original line number Original line Diff line number Diff line
@@ -64,23 +64,15 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg) 
			goto out;

			goto out;

		}

		}





		units = 0;

		if (IS_CHERRYVIEW(dev) && czcount_30ns == 1) {

		div = 1000000ULL;



		if (IS_CHERRYVIEW(dev)) {

			/* Special case for 320Mhz */

			/* Special case for 320Mhz */

			if (czcount_30ns == 1) {

			div = 10000000ULL;

			div = 10000000ULL;

			units = 3125ULL;

			units = 3125ULL;

		} else {

		} else {

				/* chv counts are one less */

			czcount_30ns += 1;

			czcount_30ns += 1;

			div = 1000000ULL;

			units = DIV_ROUND_UP_ULL(30ULL * bias, czcount_30ns);

		}

		}

		}



		if (units == 0)

			units = DIV_ROUND_UP_ULL(30ULL * bias,

						 (u64)czcount_30ns);





		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)

		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)

			units <<= 8;

			units <<= 8;