Merge "ARM: dts: msm: Enable LT9611 for SDM845 RB3" into msm-4.9 (66c284b9) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+15 −0

Original line number	Original line	Diff line number	Diff line
	@@ -893,6 +893,21 @@
	};		};
	};		};

			ext_bridge_mux {
			lt9611_pins: lt9611_pins {
			mux {
			pins = "gpio84", "gpio128", "gpio89";
			function = "gpio";
			};

			config {
			pins = "gpio84", "gpio128", "gpio89";
			bias-disable = <0>; /* no pull */
			drive-strength = <8>;
			};
			};
			};

	sec_aux_pcm {		sec_aux_pcm {
	sec_aux_pcm_sleep: sec_aux_pcm_sleep {		sec_aux_pcm_sleep: sec_aux_pcm_sleep {
	mux {		mux {

arch/arm64/boot/dts/qcom/sdm845-sde-display.dtsi

+23 −0

Original line number	Original line	Diff line number	Diff line
	@@ -527,6 +527,29 @@
	ibb-supply = <&ibb_regulator>;		ibb-supply = <&ibb_regulator>;
	};		};

			ext_dsi_bridge_display: qcom,dsi-display@19 {
			compatible = "qcom,dsi-display";
			label = "ext_dsi_bridge_display";
			qcom,display-type = "primary";

			qcom,dsi-ctrl = <&mdss_dsi0>;
			qcom,dsi-phy = <&mdss_dsi_phy0>;
			clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
			<&mdss_dsi0_pll PCLK_MUX_0_CLK>;
			clock-names = "mux_byte_clk", "mux_pixel_clk";

			ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
			reg = <0>;
			ext_dsi_out: endpoint {
			};
			};
			};
			};

	sde_wb: qcom,wb-display@0 {		sde_wb: qcom,wb-display@0 {
	compatible = "qcom,wb-display";		compatible = "qcom,wb-display";
	cell-index = <0>;		cell-index = <0>;

arch/arm64/boot/dts/qcom/sdm845-v2.1-rb3.dtsi

+93 −0

Original line number	Original line	Diff line number	Diff line
	@@ -204,3 +204,96 @@
	&ipa_hw {		&ipa_hw {
	status="disabled";		status="disabled";
	};		};

			&dsi_nt35597_truly_dsc_cmd_display {
			/delete-property/ qcom,dsi-display-active;
			};

			&mdss_mdp {
			bridges = <&lt9611>;
			};

			&soc {
			lt9611_vcc_eldo: lt9611-gpio-regulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "lt9611_vcc_eldo";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			regulator-enable-ramp-delay = <233>;
			gpio = <&tlmm 89 0>;
			enable-active-high;
			};
			};

			&qupv3_se10_i2c {
			status = "ok";
			lt9611: lt,lt9611@3b {
			compatible = "lt,lt9611";
			reg = <0x3b>;
			interrupt-parent = <&tlmm>;
			interrupts = <84 0>;
			interrupt-names = "lt_irq";
			lt,irq-gpio = <&tlmm 84 0x0>;
			lt,reset-gpio = <&tlmm 128 0x0>;
			lt,non-pluggable;
			lt,preferred-mode = "1920x1080";

			pinctrl-names = "default";
			pinctrl-0 = <&lt9611_pins>;

			vdd-supply = <&lt9611_vcc_eldo>;
			lt,supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			lt,supply-entry@0 {
			reg = <0>;
			lt,supply-name = "vdd";
			lt,supply-min-voltage = <1800000>;
			lt,supply-max-voltage = <1800000>;
			lt,supply-enable-load = <200000>;
			lt,supply-post-on-sleep = <150>;
			};
			};

			lt,customize-modes {
			lt,customize-mode-id@0 {
			lt,mode-h-active = <1920>;
			lt,mode-h-front-porch = <88>;
			lt,mode-h-pulse-width = <44>;
			lt,mode-h-back-porch = <148>;
			lt,mode-h-active-high;
			lt,mode-v-active = <1080>;
			lt,mode-v-front-porch = <4>;
			lt,mode-v-pulse-width = <5>;
			lt,mode-v-back-porch = <36>;
			lt,mode-v-active-high;
			lt,mode-refresh-rate = <60>;
			lt,mode-clock-in-khz = <148500>;
			};
			};

			ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
			reg = <0>;
			lt9611_in: endpoint {
			remote-endpoint = <&ext_dsi_out>;
			};
			};
			};
			};
			};

			&ext_dsi_bridge_display {
			qcom,dsi-display-active;
			ports {
			port@0 {
			ext_dsi_out: endpoint {
			remote-endpoint = <&lt9611_in>;
			};
			};
			};
			};