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Commit 66b0fe34 authored by Sahitya Tummala's avatar Sahitya Tummala Committed by Xiaonian Wang
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mmc: sdhci-msm: wait for SW reset to be complete 



Wait for SW reset to be complete before proceeding further
in probe. Otherwise, any register writes immediately
after the reset would be ignored/reset.

Change-Id: If1c7f5debfca6f45a0fdb08bc759ad04b96fd86c
Signed-off-by: default avatarSahitya Tummala <stummala@codeaurora.org>
[xiaonian@codeaurora.org: fix trivial merge conflict]
Signed-off-by: default avatarXiaonian Wang <xiaonian@codeaurora.org>
parent 8dce5c62

drivers/mmc/host/sdhci-msm.c

+17 −1
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include <linux/mmc/mmc.h>

#include <linux/mmc/mmc.h>

#include <linux/mmc/slot-gpio.h>

#include <linux/mmc/slot-gpio.h>

#include <linux/dma-mapping.h>

#include <linux/dma-mapping.h>

#include <linux/iopoll.h>

#include <linux/msm-bus.h>

#include <linux/msm-bus.h>





#include "sdhci-pltfm.h"

#include "sdhci-pltfm.h"
@@ -1812,6 +1813,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	struct resource *core_memres = NULL;

	struct resource *core_memres = NULL;

	int ret = 0, pwr_irq = 0, dead = 0;

	int ret = 0, pwr_irq = 0, dead = 0;

	u16 host_version;

	u16 host_version;

	u32 pwr;





	pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__);

	pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__);

	msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host),

	msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host),
@@ -1920,7 +1922,21 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	}

	}





	/* Set SW_RST bit in POWER register (Offset 0x0) */

	/* Set SW_RST bit in POWER register (Offset 0x0) */

	writel_relaxed(CORE_SW_RST, msm_host->core_mem + CORE_POWER);

	writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |

			CORE_SW_RST, msm_host->core_mem + CORE_POWER);

	/*

	 * SW reset can take upto 10HCLK + 15MCLK cycles.

	 * Calculating based on min clk rates (hclk = 27MHz,

	 * mclk = 400KHz) it comes to ~40us. Let's poll for

	 * max. 1ms for reset completion.

	 */

	ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER,

			pwr, !(pwr & CORE_SW_RST), 100, 10);



	if (ret) {

		dev_err(&pdev->dev, "reset failed (%d)\n", ret);

		goto vreg_deinit;

	}

	/* Set HC_MODE_EN bit in HC_MODE register */

	/* Set HC_MODE_EN bit in HC_MODE register */

	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));

	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));