Loading arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,7 @@ reg = <0x150c5000 0x1000>, <0x150c2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; }; Loading @@ -140,6 +141,7 @@ reg = <0x150c9000 0x1000>, <0x150c2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; }; Loading @@ -150,6 +152,7 @@ reg = <0x150cd000 0x1000>, <0x150c2210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; }; Loading @@ -160,6 +163,7 @@ reg = <0x150d1000 0x1000>, <0x150c2218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; }; Loading @@ -170,6 +174,7 @@ reg = <0x150d5000 0x1000>, <0x150c2220 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; }; Loading @@ -180,6 +185,7 @@ reg = <0x150d9000 0x1000>, <0x150c2228 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; /* No GDSC */ }; Loading @@ -189,6 +195,7 @@ reg = <0x150dd000 0x1000>, <0x150c2230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; }; Loading @@ -199,6 +206,7 @@ reg = <0x150e1000 0x1000>, <0x150c2238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; }; Loading Loading
arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi +8 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,7 @@ reg = <0x150c5000 0x1000>, <0x150c2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; }; Loading @@ -140,6 +141,7 @@ reg = <0x150c9000 0x1000>, <0x150c2208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; }; Loading @@ -150,6 +152,7 @@ reg = <0x150cd000 0x1000>, <0x150c2210 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; }; Loading @@ -160,6 +163,7 @@ reg = <0x150d1000 0x1000>, <0x150c2218 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0xc00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; }; Loading @@ -170,6 +174,7 @@ reg = <0x150d5000 0x1000>, <0x150c2220 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; }; Loading @@ -180,6 +185,7 @@ reg = <0x150d9000 0x1000>, <0x150c2228 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; /* No GDSC */ }; Loading @@ -189,6 +195,7 @@ reg = <0x150dd000 0x1000>, <0x150c2230 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; }; Loading @@ -199,6 +206,7 @@ reg = <0x150e1000 0x1000>, <0x150c2238 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1c00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; }; Loading