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Commit 665bb114 authored by Mike Turquette's avatar Mike Turquette
Browse files

Merge tag 'zynq-clk-for-3.16' of git://git.xilinx.com/linux-xlnx into clk-next-zynq 

arm: Xilinx Zynq clk patches for v3.16

- Keep debug clocks in bootup state
- Fix email address in si570
parents d15998e0 44731f5d

drivers/clk/clk-si570.c

+1 −1
Original line number Diff line number Diff line
@@ -526,6 +526,6 @@ static struct i2c_driver si570_driver = { 
module_i2c_driver(si570_driver);



MODULE_AUTHOR("Guenter Roeck <guenter.roeck@ericsson.com>");

MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");

MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");

MODULE_DESCRIPTION("Si570 driver");

MODULE_LICENSE("GPL");

drivers/clk/zynq/clkc.c

+12 −0
Original line number Diff line number Diff line
@@ -53,6 +53,9 @@ static void __iomem *zynq_clkc_base; 


#define NUM_MIO_PINS	54



#define DBG_CLK_CTRL_CLKACT_TRC		BIT(0)

#define DBG_CLK_CTRL_CPU_1XCLKACT	BIT(1)



enum zynq_clk {

	armpll, ddrpll, iopll,

	cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
@@ -499,6 +502,15 @@ static void __init zynq_clk_setup(struct device_node *np) 
			clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,

			&dbgclk_lock);



	/* leave debug clocks in the state the bootloader set them up to */

	tmp = clk_readl(SLCR_DBG_CLK_CTRL);

	if (tmp & DBG_CLK_CTRL_CLKACT_TRC)

		if (clk_prepare_enable(clks[dbg_trc]))

			pr_warn("%s: trace clk enable failed\n", __func__);

	if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)

		if (clk_prepare_enable(clks[dbg_apb]))

			pr_warn("%s: debug APB clk enable failed\n", __func__);



	/* One gated clock for all APER clocks. */

	clks[dma] = clk_register_gate(NULL, clk_output_name[dma],

			clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,