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Commit 664ee63a authored by Harshdeep Dhatt's avatar Harshdeep Dhatt Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Set preemption OOB when reading the write pointer 



OOB is needed because the GPU maybe in IFPC. And reading a fenced
register in FENCE drop mode causes a FENCE error interrupt and
the read returns with the signature value. For the read to go
through, the GPU must be ON. For this, add a new OOB bit to be
used exclusively for the preemption path.

Change-Id: I458559b74bf6f5438e0c77efbbdf9ae11615ee13
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 59a69575

drivers/gpu/msm/adreno_a6xx_preempt.c

+25 −0
Original line number Diff line number Diff line
@@ -35,6 +35,25 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) 
	struct adreno_ringbuffer *rb = adreno_dev->cur_rb;

	unsigned int wptr;

	unsigned long flags;

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	/*

	 * Need to make sure GPU is up before we read the

	 * WPTR as fence doesn't wake GPU on read operation.

	 */

	if (in_interrupt() == 0) {

		int status;



		if (gpudev->oob_set) {

			status = gpudev->oob_set(adreno_dev,

				OOB_PREEMPTION_SET_MASK,

				OOB_PREEMPTION_CHECK_MASK,

				OOB_PREEMPTION_CLEAR_MASK);

			if (status)

				return;

		}

	}





	spin_lock_irqsave(&rb->preempt_lock, flags);
@@ -55,6 +74,12 @@ static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer) 
			msecs_to_jiffies(adreno_drawobj_timeout);



	spin_unlock_irqrestore(&rb->preempt_lock, flags);



	if (in_interrupt() == 0) {

		if (gpudev->oob_clear)

			gpudev->oob_clear(adreno_dev,

				OOB_PREEMPTION_CLEAR_MASK);

	}

}



static inline bool adreno_move_preempt_state(struct adreno_device *adreno_dev,

drivers/gpu/msm/kgsl_gmu.h

+3 −0
Original line number Diff line number Diff line
@@ -81,6 +81,9 @@ 
#define OOB_PERFCNTR_SET_MASK		BIT(17)

#define OOB_PERFCNTR_CHECK_MASK		BIT(25)

#define OOB_PERFCNTR_CLEAR_MASK		BIT(25)

#define OOB_PREEMPTION_SET_MASK		BIT(18)

#define OOB_PREEMPTION_CHECK_MASK	BIT(26)

#define OOB_PREEMPTION_CLEAR_MASK	BIT(26)



/*

 * Wait time before trying to write the register again.