Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 664326f8 authored by A.Sunil Kamath's avatar A.Sunil Kamath Committed by Daniel Vetter
Browse files

drm/i915/bxt: Implement enable/disable for Display C9 state 



v2: Modified as per review comments from Imre
- Mention enabling instead of allowing in the debug trace and
  remove unnecessary comments.

v3:
- Rebase to latest.
- Move DC9-related functions from intel_display.c to intel_runtime_pm.c.

v4: (imre)
- remove DC5 disabling, it's a nop at this point
- squashed in Suketu's "Assert the requirements to enter or exit DC9"
  patch
- remove check for RUNTIME_PM from assert_can_enable_dc9, it's not a
  dependency

Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v3)
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarSagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent eee21566

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -7059,6 +7059,11 @@ enum skl_disp_power_wells { 
#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)

#define   BXT_DE_PLL_PLL_ENABLE		(1 << 31)

#define   BXT_DE_PLL_LOCK		(1 << 30)

#define   BXT_DE_PLL_LOCK		(1 << 30)





/* GEN9 DC */

#define DC_STATE_EN			0x45504

#define  DC_STATE_EN_UPTO_DC5		(1<<0)

#define  DC_STATE_EN_DC9		(1<<3)



/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,

/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,

 * since on HSW we can't write to it using I915_WRITE. */

 * since on HSW we can't write to it using I915_WRITE. */

#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)

#define D_COMP_HSW			(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -1117,6 +1117,8 @@ void broxton_uninit_cdclk(struct drm_device *dev); 
void broxton_set_cdclk(struct drm_device *dev, int frequency);

void broxton_set_cdclk(struct drm_device *dev, int frequency);

void broxton_ddi_phy_init(struct drm_device *dev);

void broxton_ddi_phy_init(struct drm_device *dev);

void broxton_ddi_phy_uninit(struct drm_device *dev);

void broxton_ddi_phy_uninit(struct drm_device *dev);

void bxt_enable_dc9(struct drm_i915_private *dev_priv);

void bxt_disable_dc9(struct drm_i915_private *dev_priv);

void intel_dp_get_m_n(struct intel_crtc *crtc,

void intel_dp_get_m_n(struct intel_crtc *crtc,

		      struct intel_crtc_state *pipe_config);

		      struct intel_crtc_state *pipe_config);

void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);

void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);

drivers/gpu/drm/i915/intel_runtime_pm.c

+66 −0
Original line number Original line Diff line number Diff line
@@ -351,6 +351,72 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, 
	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\

	BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |	\

	BIT(POWER_DOMAIN_INIT))

	BIT(POWER_DOMAIN_INIT))





static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;



	WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");

	WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),

		"DC9 already programmed to be enabled.\n");

	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,

		"DC5 still not disabled to enable DC9.\n");

	WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");

	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");



	 /*

	  * TODO: check for the following to verify the conditions to enter DC9

	  * state are satisfied:

	  * 1] Check relevant display engine registers to verify if mode set

	  * disable sequence was followed.

	  * 2] Check if display uninitialize sequence is initialized.

	  */

}



static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)

{

	WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");

	WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),

		"DC9 already programmed to be disabled.\n");

	WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,

		"DC5 still not disabled.\n");



	 /*

	  * TODO: check for the following to verify DC9 state was indeed

	  * entered before programming to disable it:

	  * 1] Check relevant display engine registers to verify if mode

	  *  set disable sequence was followed.

	  * 2] Check if display uninitialize sequence is initialized.

	  */

}



void bxt_enable_dc9(struct drm_i915_private *dev_priv)

{

	uint32_t val;



	assert_can_enable_dc9(dev_priv);



	DRM_DEBUG_KMS("Enabling DC9\n");



	val = I915_READ(DC_STATE_EN);

	val |= DC_STATE_EN_DC9;

	I915_WRITE(DC_STATE_EN, val);

	POSTING_READ(DC_STATE_EN);

}



void bxt_disable_dc9(struct drm_i915_private *dev_priv)

{

	uint32_t val;



	assert_can_disable_dc9(dev_priv);



	DRM_DEBUG_KMS("Disabling DC9\n");



	val = I915_READ(DC_STATE_EN);

	val &= ~DC_STATE_EN_DC9;

	I915_WRITE(DC_STATE_EN, val);

	POSTING_READ(DC_STATE_EN);

}



static void skl_set_power_well(struct drm_i915_private *dev_priv,

static void skl_set_power_well(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well, bool enable)

			struct i915_power_well *power_well, bool enable)

{

{