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Commit 6623b7bb authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable UFS support for sdm670"

parents ab5fe500 099af9cb
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+32 −0
Original line number Diff line number Diff line
@@ -45,3 +45,35 @@
&qupv3_se6_4uart {
	status = "disabled";
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	vdda-phy-supply = <&pm660l_l1>; /* 0.88v */
	vdda-pll-supply = <&pm660_l1>; /* 1.2v */
	vdda-phy-max-microamp = <62900>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;
	scsi-cmd-timeout = <300000>;

	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm660l_l4>;
	vccq2-supply = <&pm660_l8>;
	vcc-max-microamp = <600000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm660_l1>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,disable-lpm;
	rpm-level = <0>;
	spm-level = <0>;
	status = "ok";
};
+64 −1
Original line number Diff line number Diff line
@@ -27,7 +27,9 @@
	qcom,msm-id = <336 0x0>;
	interrupt-parent = <&intc>;

	aliases { };
	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
	};

	cpus {
		#address-cells = <2>;
@@ -975,6 +977,67 @@
		#interrupt-cells = <4>;
		cell-index = <0>;
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <1>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>;
		interrupts = <0 265 0>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";

		lanes-per-direction = <1>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk";
		clocks =
			<&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
			<&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
		freq-table-hz =
			<50000000 200000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>;

		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "core_reset";

		status = "disabled";
	};
};

#include "sdm670-pinctrl.dtsi"