[MIPS] rbtx4938: misc cleanups (66140c8e) · Commits · e / devices / android_kernel_fairphone_FP3

arch/mips/tx4938/common/dbgio.c

+1 −3

Original line number	Original line	Diff line number	Diff line
	@@ -31,9 +31,7 @@
	* Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>		* Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
	*/		*/

	#include <asm/mipsregs.h>		#include <linux/types>
	#include <asm/system.h>
	#include <asm/tx4938/tx4938_mips.h>

	extern u8 txx9_sio_kdbg_rd(void);		extern u8 txx9_sio_kdbg_rd(void);
	extern int txx9_sio_kdbg_wr( u8 ch );		extern int txx9_sio_kdbg_wr( u8 ch );

arch/mips/tx4938/common/prom.c

+3 −8

Original line number	Original line	Diff line number	Diff line
	@@ -13,13 +13,8 @@
	*/		*/

	#include <linux/init.h>		#include <linux/init.h>
	#include <linux/mm.h>		#include <linux/types.h>
	#include <linux/sched.h>		#include <linux/io.h>
	#include <linux/bootmem.h>

	#include <asm/addrspace.h>
	#include <asm/bootinfo.h>
	#include <asm/tx4938/tx4938.h>

	static unsigned int __init		static unsigned int __init
	tx4938_process_sdccr(u64 * addr)		tx4938_process_sdccr(u64 * addr)
	@@ -35,7 +30,7 @@ tx4938_process_sdccr(u64 * addr)
	unsigned int bc = 4;		unsigned int bc = 4;
	unsigned int msize = 0;		unsigned int msize = 0;

	val = (((vu64 ) (addr)));		val = ____raw_readq((void __iomem *)addr);

	/* MVMCP -- need #defs for these bits masks */		/* MVMCP -- need #defs for these bits masks */
	sdccr_ce = ((val & (1 << 10)) >> 10);		sdccr_ce = ((val & (1 << 10)) >> 10);

arch/mips/tx4938/toshiba_rbtx4938/irq.c

+10 −36

Original line number	Original line	Diff line number	Diff line
	@@ -67,24 +67,7 @@ IRQ Device
	63 RBTX4938-IOC/07 SWINT		63 RBTX4938-IOC/07 SWINT
	*/		*/
	#include <linux/init.h>		#include <linux/init.h>
	#include <linux/kernel.h>
	#include <linux/types.h>
	#include <linux/mm.h>
	#include <linux/swap.h>
	#include <linux/ioport.h>
	#include <linux/sched.h>
	#include <linux/interrupt.h>		#include <linux/interrupt.h>
	#include <linux/pci.h>
	#include <linux/timex.h>
	#include <asm/bootinfo.h>
	#include <asm/page.h>
	#include <asm/io.h>
	#include <asm/irq.h>
	#include <asm/processor.h>
	#include <asm/reboot.h>
	#include <asm/time.h>
	#include <asm/wbflush.h>
	#include <linux/bootmem.h>
	#include <asm/tx4938/rbtx4938.h>		#include <asm/tx4938/rbtx4938.h>

	static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);		static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
	@@ -99,21 +82,16 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
	.unmask = toshiba_rbtx4938_irq_ioc_enable,		.unmask = toshiba_rbtx4938_irq_ioc_enable,
	};		};

	#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
	#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a

	int		int
	toshiba_rbtx4938_irq_nested(int sw_irq)		toshiba_rbtx4938_irq_nested(int sw_irq)
	{		{
	u8 level3;		u8 level3;

	level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;		level3 = readb(rbtx4938_imstat_addr);
	if (level3) {		if (level3)
	/* must use fls so onboard ATA has priority */		/* must use fls so onboard ATA has priority */
	sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;		sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
	}

	wbflush();
	return sw_irq;		return sw_irq;
	}		}

	@@ -144,25 +122,23 @@ toshiba_rbtx4938_irq_ioc_init(void)
	static void		static void
	toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)		toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
	{		{
	volatile unsigned char v;		unsigned char v;

	v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);		v = readb(rbtx4938_imask_addr);
	v \|= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));		v \|= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
	TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);		writeb(v, rbtx4938_imask_addr);
	mmiowb();		mmiowb();
	TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
	}		}

	static void		static void
	toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)		toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
	{		{
	volatile unsigned char v;		unsigned char v;

	v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);		v = readb(rbtx4938_imask_addr);
	v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));		v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
	TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);		writeb(v, rbtx4938_imask_addr);
	mmiowb();		mmiowb();
	TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
	}		}

	void __init arch_init_irq(void)		void __init arch_init_irq(void)
	@@ -174,14 +150,12 @@ void __init arch_init_irq(void)
	/* all IRC interrupt mode are Low Active. */		/* all IRC interrupt mode are Low Active. */

	/* mask all IOC interrupts */		/* mask all IOC interrupts */
	*rbtx4938_imask_ptr = 0;		writeb(0, rbtx4938_imask_addr);

	/* clear SoftInt interrupts */		/* clear SoftInt interrupts */
	*rbtx4938_softint_ptr = 0;		writeb(0, rbtx4938_softint_addr);
	tx4938_irq_init();		tx4938_irq_init();
	toshiba_rbtx4938_irq_ioc_init();		toshiba_rbtx4938_irq_ioc_init();
	/* Onboard 10M Ether: High Active */		/* Onboard 10M Ether: High Active */
	set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);		set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);

	wbflush();
	}		}

arch/mips/tx4938/toshiba_rbtx4938/setup.c

+29 −37

Original line number	Original line	Diff line number	Diff line
	@@ -23,7 +23,6 @@
	#include <linux/clk.h>		#include <linux/clk.h>
	#include <linux/gpio.h>		#include <linux/gpio.h>

	#include <asm/wbflush.h>
	#include <asm/reboot.h>		#include <asm/reboot.h>
	#include <asm/time.h>		#include <asm/time.h>
	#include <asm/txx9tmr.h>		#include <asm/txx9tmr.h>
	@@ -91,12 +90,11 @@ void rbtx4938_machine_restart(char *command)
	local_irq_disable();		local_irq_disable();

	printk("Rebooting...");		printk("Rebooting...");
	*rbtx4938_softresetlock_ptr = 1;		writeb(1, rbtx4938_softresetlock_addr);
	*rbtx4938_sfvol_ptr = 1;		writeb(1, rbtx4938_sfvol_addr);
	*rbtx4938_softreset_ptr = 1;		writeb(1, rbtx4938_softreset_addr);
	wbflush();		while(1)
			;
	while(1);
	}		}

	void __init		void __init
	@@ -488,7 +486,7 @@ static int __init tx4938_pcibios_init(void)
	}		}

	/* Reset PCI Bus */		/* Reset PCI Bus */
	*rbtx4938_pcireset_ptr = 0;		writeb(0, rbtx4938_pcireset_addr);
	/* Reset PCIC */		/* Reset PCIC */
	tx4938_ccfgptr->clkctr \|= TX4938_CLKCTR_PCIRST;		tx4938_ccfgptr->clkctr \|= TX4938_CLKCTR_PCIRST;
	if (txboard_pci66_mode > 0)		if (txboard_pci66_mode > 0)
	@@ -496,8 +494,8 @@ static int __init tx4938_pcibios_init(void)
	mdelay(10);		mdelay(10);
	/* clear PCIC reset */		/* clear PCIC reset */
	tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;		tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
	*rbtx4938_pcireset_ptr = 1;		writeb(1, rbtx4938_pcireset_addr);
	wbflush();		mmiowb();
	tx4938_report_pcic_status1(tx4938_pcicptr);		tx4938_report_pcic_status1(tx4938_pcicptr);

	tx4938_report_pciclk();		tx4938_report_pciclk();
	@@ -505,15 +503,15 @@ static int __init tx4938_pcibios_init(void)
	if (txboard_pci66_mode == 0 &&		if (txboard_pci66_mode == 0 &&
	txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {		txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
	/* Reset PCI Bus */		/* Reset PCI Bus */
	*rbtx4938_pcireset_ptr = 0;		writeb(0, rbtx4938_pcireset_addr);
	/* Reset PCIC */		/* Reset PCIC */
	tx4938_ccfgptr->clkctr \|= TX4938_CLKCTR_PCIRST;		tx4938_ccfgptr->clkctr \|= TX4938_CLKCTR_PCIRST;
	tx4938_pciclk66_setup();		tx4938_pciclk66_setup();
	mdelay(10);		mdelay(10);
	/* clear PCIC reset */		/* clear PCIC reset */
	tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;		tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
	*rbtx4938_pcireset_ptr = 1;		writeb(1, rbtx4938_pcireset_addr);
	wbflush();		mmiowb();
	/* Reinitialize PCIC */		/* Reinitialize PCIC */
	tx4938_report_pciclk();		tx4938_report_pciclk();
	tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);		tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
	@@ -774,8 +772,9 @@ void __init tx4938_board_setup(void)
	txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);		txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);

	/* enable DMA */		/* enable DMA */
	TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);		for (i = 0; i < 2; i++)
	TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);		____raw_writeq(TX4938_DMA_MCR_MSTEN,
			(void __iomem *)(TX4938_DMA_REG(i) + 0x50));

	/* PIO */		/* PIO */
	__raw_writel(0, &tx4938_pioptr->maskcpu);		__raw_writel(0, &tx4938_pioptr->maskcpu);
	@@ -861,10 +860,6 @@ void __init plat_mem_setup(void)
	if (txx9_master_clock == 0)		if (txx9_master_clock == 0)
	txx9_master_clock = 25000000; /* 25MHz */		txx9_master_clock = 25000000; /* 25MHz */
	tx4938_board_setup();		tx4938_board_setup();
	/* setup serial stuff */
	TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
	TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */

	#ifndef CONFIG_PCI		#ifndef CONFIG_PCI
	set_io_port_base(RBTX4938_ETHER_BASE);		set_io_port_base(RBTX4938_ETHER_BASE);
	#endif		#endif
	@@ -930,16 +925,16 @@ void __init plat_mem_setup(void)
	pcfg = tx4938_ccfgptr->pcfg; /* updated */		pcfg = tx4938_ccfgptr->pcfg; /* updated */
	/* fixup piosel */		/* fixup piosel */
	if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==		if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==
	TX4938_PCFG_ATA_SEL) {		TX4938_PCFG_ATA_SEL)
	rbtx4938_piosel_ptr = (rbtx4938_piosel_ptr & 0x03) \| 0x04;		writeb((readb(rbtx4938_piosel_addr) & 0x03) \| 0x04,
	}		rbtx4938_piosel_addr);
	else if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==		else if ((pcfg & (TX4938_PCFG_ATA_SEL \| TX4938_PCFG_NDF_SEL)) ==
	TX4938_PCFG_NDF_SEL) {		TX4938_PCFG_NDF_SEL)
	rbtx4938_piosel_ptr = (rbtx4938_piosel_ptr & 0x03) \| 0x08;		writeb((readb(rbtx4938_piosel_addr) & 0x03) \| 0x08,
	}		rbtx4938_piosel_addr);
	else {		else
	*rbtx4938_piosel_ptr &= ~(0x08 \| 0x04);		writeb(readb(rbtx4938_piosel_addr) & ~(0x08 \| 0x04),
	}		rbtx4938_piosel_addr);

	rbtx4938_fpga_resource.name = "FPGA Registers";		rbtx4938_fpga_resource.name = "FPGA Registers";
	rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);		rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
	@@ -948,17 +943,14 @@ void __init plat_mem_setup(void)
	if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))		if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
	printk("request resource for fpga failed\n");		printk("request resource for fpga failed\n");

	/* disable all OnBoard I/O interrupts */
	*rbtx4938_imask_ptr = 0;

	_machine_restart = rbtx4938_machine_restart;		_machine_restart = rbtx4938_machine_restart;
	_machine_halt = rbtx4938_machine_halt;		_machine_halt = rbtx4938_machine_halt;
	pm_power_off = rbtx4938_machine_power_off;		pm_power_off = rbtx4938_machine_power_off;

	*rbtx4938_led_ptr = 0xff;		writeb(0xff, rbtx4938_led_addr);
	printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);		printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
	printk(" DIPSW:%02x,%02x\n",		readb(rbtx4938_fpga_rev_addr),
	rbtx4938_dipsw_ptr, rbtx4938_bdipsw_ptr);		readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
	}		}

	static int __init rbtx4938_ne_init(void)		static int __init rbtx4938_ne_init(void)
	@@ -1000,12 +992,12 @@ static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
	u8 val;		u8 val;
	unsigned long flags;		unsigned long flags;
	spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);		spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
	val = *rbtx4938_spics_ptr;		val = readb(rbtx4938_spics_addr);
	if (value)		if (value)
	val \|= 1 << offset;		val \|= 1 << offset;
	else		else
	val &= ~(1 << offset);		val &= ~(1 << offset);
	*rbtx4938_spics_ptr = val;		writeb(val, rbtx4938_spics_addr);
	mmiowb();		mmiowb();
	spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);		spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
	}		}

include/asm-mips/tx4938/rbtx4938.h

+20 −38

Original line number	Original line	Diff line number	Diff line
	@@ -67,44 +67,26 @@
	#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)		#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
	#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)		#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)

	#define rbtx4938_fpga_rev_ptr \		#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
	((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)		#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
	#define rbtx4938_led_ptr \		#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
	((volatile unsigned char *)RBTX4938_LED_ADDR)		#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
	#define rbtx4938_dipsw_ptr \		#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
	((volatile unsigned char *)RBTX4938_DIPSW_ADDR)		#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
	#define rbtx4938_bdipsw_ptr \		#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
	((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)		#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
	#define rbtx4938_imask_ptr \		#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
	((volatile unsigned char *)RBTX4938_IMASK_ADDR)		#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
	#define rbtx4938_imask2_ptr \		#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
	((volatile unsigned char *)RBTX4938_IMASK2_ADDR)		#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
	#define rbtx4938_intpol_ptr \		#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
	((volatile unsigned char *)RBTX4938_INTPOL_ADDR)		#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
	#define rbtx4938_istat_ptr \		#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
	((volatile unsigned char *)RBTX4938_ISTAT_ADDR)		#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
	#define rbtx4938_istat2_ptr \		#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
	((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)		#define rbtx4938_softresetlock_addr \
	#define rbtx4938_imstat_ptr \		((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
	((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)		#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
	#define rbtx4938_imstat2_ptr \
	((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
	#define rbtx4938_softint_ptr \
	((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
	#define rbtx4938_piosel_ptr \
	((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
	#define rbtx4938_spics_ptr \
	((volatile unsigned char *)RBTX4938_SPICS_ADDR)
	#define rbtx4938_sfpwr_ptr \
	((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
	#define rbtx4938_sfvol_ptr \
	((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
	#define rbtx4938_softreset_ptr \
	((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
	#define rbtx4938_softresetlock_ptr \
	((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
	#define rbtx4938_pcireset_ptr \
	((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)

	/*		/*
	* IRQ mappings		* IRQ mappings