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Commit 65fcf668 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add query for number of active CUs 



Query to find out how many compute units on a GPU.
Useful for OpenCL usermode drivers.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 478b6e72

drivers/gpu/drm/radeon/cik.c

+11 −1
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ extern int sumo_rlc_init(struct radeon_device *rdev); 
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);

extern void si_rlc_reset(struct radeon_device *rdev);

extern void si_init_uvd_internal_cg(struct radeon_device *rdev);

static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);

extern int cik_sdma_resume(struct radeon_device *rdev);

extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);

extern void cik_sdma_fini(struct radeon_device *rdev);
@@ -3257,7 +3258,7 @@ static void cik_gpu_init(struct radeon_device *rdev) 
	u32 mc_shared_chmap, mc_arb_ramcfg;

	u32 hdp_host_path_cntl;

	u32 tmp;

	int i, j;

	int i, j, k;



	switch (rdev->family) {

	case CHIP_BONAIRE:
@@ -3446,6 +3447,15 @@ static void cik_gpu_init(struct radeon_device *rdev) 
		     rdev->config.cik.max_sh_per_se,

		     rdev->config.cik.max_backends_per_se);



	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {

		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {

			for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {

				rdev->config.cik.active_cus +=

					hweight32(cik_get_cu_active_bitmap(rdev, i, j));

			}

		}

	}



	/* set HW defaults for 3D engine */

	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));

drivers/gpu/drm/radeon/evergreen.c

+12 −0
Original line number Diff line number Diff line
@@ -3337,6 +3337,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
			disabled_rb_mask &= ~(1 << i);

	}



	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {

		u32 simd_disable_bitmap;



		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

		simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;

		tmp <<= 16;

		tmp |= simd_disable_bitmap;

	}

	rdev->config.evergreen.active_simds = hweight32(~tmp);



	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

drivers/gpu/drm/radeon/ni.c

+12 −0
Original line number Diff line number Diff line
@@ -1057,6 +1057,18 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
			disabled_rb_mask &= ~(1 << i);

	}



	for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {

		u32 simd_disable_bitmap;



		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;

		simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;

		tmp <<= 16;

		tmp |= simd_disable_bitmap;

	}

	rdev->config.cayman.active_simds = hweight32(~tmp);



	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

drivers/gpu/drm/radeon/r600.c

+3 −0
Original line number Diff line number Diff line
@@ -1958,6 +1958,9 @@ static void r600_gpu_init(struct radeon_device *rdev) 
	if (tmp < rdev->config.r600.max_simds) {

		rdev->config.r600.max_simds = tmp;

	}

	tmp = rdev->config.r600.max_simds -

		r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);

	rdev->config.r600.active_simds = tmp;



	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;

	tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;

drivers/gpu/drm/radeon/radeon.h

+6 −0
Original line number Diff line number Diff line
@@ -1932,6 +1932,7 @@ struct r600_asic { 
	unsigned		tiling_group_size;

	unsigned		tile_config;

	unsigned		backend_map;

	unsigned		active_simds;

};



struct rv770_asic {
@@ -1957,6 +1958,7 @@ struct rv770_asic { 
	unsigned		tiling_group_size;

	unsigned		tile_config;

	unsigned		backend_map;

	unsigned		active_simds;

};



struct evergreen_asic {
@@ -1983,6 +1985,7 @@ struct evergreen_asic { 
	unsigned tiling_group_size;

	unsigned tile_config;

	unsigned backend_map;

	unsigned active_simds;

};



struct cayman_asic {
@@ -2021,6 +2024,7 @@ struct cayman_asic { 
	unsigned multi_gpu_tile_size;



	unsigned tile_config;

	unsigned active_simds;

};



struct si_asic {
@@ -2051,6 +2055,7 @@ struct si_asic { 


	unsigned tile_config;

	uint32_t tile_mode_array[32];

	uint32_t active_cus;

};



struct cik_asic {
@@ -2082,6 +2087,7 @@ struct cik_asic { 
	unsigned tile_config;

	uint32_t tile_mode_array[32];

	uint32_t macrotile_mode_array[16];

	uint32_t active_cus;

};



union radeon_asic_config {