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Commit 65abef72 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "clk: msm: mdss: add HDMI PLL sequence for MSM8996v2" into msm-4.8

parents 514970a6 71732577
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+579 −33

File changed.

Preview size limit exceeded, changes collapsed.

+4 −1
Original line number Diff line number Diff line
@@ -39,6 +39,9 @@ int hdmi_pll_clock_register(struct platform_device *pdev,
int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
				struct mdss_pll_resources *pll_res);

int hdmi_8996_pll_clock_register(struct platform_device *pdev,
int hdmi_8996_v1_pll_clock_register(struct platform_device *pdev,
				 struct mdss_pll_resources *pll_res);

int hdmi_8996_v2_pll_clock_register(struct platform_device *pdev,
				 struct mdss_pll_resources *pll_res);
#endif
+7 −1
Original line number Diff line number Diff line
@@ -137,6 +137,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
		pll_res->revision = 2;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) {
		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996;
	} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) {
		pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V2;
	} else {
		goto err;
	}
@@ -164,7 +166,10 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
		rc = dsi_pll_clock_register_8996(pdev, pll_res);
		break;
	case MDSS_HDMI_PLL_8996:
		rc = hdmi_8996_pll_clock_register(pdev, pll_res);
		rc = hdmi_8996_v1_pll_clock_register(pdev, pll_res);
		break;
	case MDSS_HDMI_PLL_8996_V2:
		rc = hdmi_8996_v2_pll_clock_register(pdev, pll_res);
		break;
	case MDSS_UNKNOWN_PLL:
	default:
@@ -341,6 +346,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
	{.compatible = "qcom,mdss_dsi_pll_8996"},
	{.compatible = "qcom,mdss_dsi_pll_8996_v2"},
	{.compatible = "qcom,mdss_hdmi_pll_8996"},
	{.compatible = "qcom,mdss_hdmi_pll_8996_v2"},
	{}
};

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@
enum {
	MDSS_DSI_PLL_8996,
	MDSS_HDMI_PLL_8996,
	MDSS_HDMI_PLL_8996_V2,
	MDSS_UNKNOWN_PLL,
};