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Commit 652e59b7 authored by Lloyd Atkinson's avatar Lloyd Atkinson
Browse files

drm/msm/sde: add sde_hw_blk as base for all hw block types 



Add base structure to the sde hardware block types, to begin to
move towards reference counting implementation of resource
management.

Change-Id: Id2179441cfb2f9b5fe036b0327be452fa70eb13b
Signed-off-by: default avatarLloyd Atkinson <latkinso@codeaurora.org>
parent d3b1457c

drivers/gpu/drm/msm/sde/sde_hw_cdm.c

+21 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "sde_hw_catalog.h"

#include "sde_hw_cdm.h"

#include "sde_dbg.h"

#include "sde_kms.h"



#define CDM_CSC_10_OPMODE                  0x000

#define CDM_CSC_10_BASE                    0x004
@@ -267,6 +268,11 @@ static void _setup_cdm_ops(struct sde_hw_cdm_ops *ops, 
	ops->disable = sde_hw_cdm_disable;

}



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

};



struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx,

		void __iomem *addr,

		struct sde_mdss_cfg *m,
@@ -274,6 +280,7 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx, 
{

	struct sde_hw_cdm *c;

	struct sde_cdm_cfg *cfg;

	int rc;



	c = kzalloc(sizeof(*c), GFP_KERNEL);

	if (!c)
@@ -290,8 +297,15 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx, 
	_setup_cdm_ops(&c->ops, c->cdm_hw_cap->features);

	c->hw_mdp = hw_mdp;



	rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_CDM, idx, &sde_hw_ops);

	if (rc) {

		SDE_ERROR("failed to init hw blk %d\n", rc);

		goto blk_init_error;

	}



	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,

			c->hw.blk_off + c->hw.length, c->hw.xin_id);



	/*

	 * Perform any default initialization for the chroma down module

	 * @setup default csc coefficients
@@ -299,9 +313,16 @@ struct sde_hw_cdm *sde_hw_cdm_init(enum sde_cdm idx, 
	sde_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);



	return c;



blk_init_error:

	kzfree(c);



	return ERR_PTR(rc);

}



void sde_hw_cdm_destroy(struct sde_hw_cdm *cdm)

{

	if (cdm)

		sde_hw_blk_destroy(&cdm->base);

	kfree(cdm);

}

drivers/gpu/drm/msm/sde/sde_hw_cdm.h

+2 −1
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


#include "sde_hw_mdss.h"

#include "sde_hw_top.h"

#include "sde_hw_blk.h"



struct sde_hw_cdm;
@@ -92,7 +93,7 @@ struct sde_hw_cdm_ops { 
};



struct sde_hw_cdm {

	/* base */

	struct sde_hw_blk base;

	struct sde_hw_blk_reg_map hw;



	/* chroma down */

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+20 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "sde_hwio.h"

#include "sde_hw_ctl.h"

#include "sde_dbg.h"

#include "sde_kms.h"



#define   CTL_LAYER(lm)                 \

	(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
@@ -562,12 +563,18 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
	}

};



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

};



struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,

		void __iomem *addr,

		struct sde_mdss_cfg *m)

{

	struct sde_hw_ctl *c;

	struct sde_ctl_cfg *cfg;

	int rc;



	c = kzalloc(sizeof(*c), GFP_KERNEL);

	if (!c)
@@ -586,13 +593,26 @@ struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, 
	c->mixer_count = m->mixer_count;

	c->mixer_hw_caps = m->mixer;



	rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_CTL, idx, &sde_hw_ops);

	if (rc) {

		SDE_ERROR("failed to init hw blk %d\n", rc);

		goto blk_init_error;

	}



	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,

			c->hw.blk_off + c->hw.length, c->hw.xin_id);



	return c;



blk_init_error:

	kzfree(c);



	return ERR_PTR(rc);

}



void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx)

{

	if (ctx)

		sde_hw_blk_destroy(&ctx->base);

	kfree(ctx);

}

drivers/gpu/drm/msm/sde/sde_hw_ctl.h

+4 −2
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "sde_hw_util.h"

#include "sde_hw_catalog.h"

#include "sde_hw_sspp.h"

#include "sde_hw_blk.h"



/**

 * sde_ctl_mode_sel: Interface mode selection
@@ -209,16 +210,17 @@ struct sde_hw_ctl_ops { 


/**

 * struct sde_hw_ctl : CTL PATH driver object

 * @base: hardware block base structure

 * @hw: block register map object

 * @idx: control path index

 * @ctl_hw_caps: control path capabilities

 * @caps: control path capabilities

 * @mixer_count: number of mixers

 * @mixer_hw_caps: mixer hardware capabilities

 * @pending_flush_mask: storage for pending ctl_flush managed via ops

 * @ops: operation list

 */

struct sde_hw_ctl {

	/* base */

	struct sde_hw_blk base;

	struct sde_hw_blk_reg_map hw;



	/* ctl path */

drivers/gpu/drm/msm/sde/sde_hw_dsc.c

+20 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "sde_hw_dsc.h"

#include "sde_hw_pingpong.h"

#include "sde_dbg.h"

#include "sde_kms.h"



#define DSC_COMMON_MODE	                0x000

#define DSC_ENC                         0X004
@@ -200,12 +201,18 @@ static void _setup_dsc_ops(struct sde_hw_dsc_ops *ops, 
	ops->dsc_config_thresh = sde_hw_dsc_config_thresh;

};



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

};



struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx,

		void __iomem *addr,

		struct sde_mdss_cfg *m)

{

	struct sde_hw_dsc *c;

	struct sde_dsc_cfg *cfg;

	int rc;



	c = kzalloc(sizeof(*c), GFP_KERNEL);

	if (!c)
@@ -221,13 +228,26 @@ struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx, 
	c->dsc_hw_cap = cfg;

	_setup_dsc_ops(&c->ops, c->dsc_hw_cap->features);



	rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_DSC, idx, &sde_hw_ops);

	if (rc) {

		SDE_ERROR("failed to init hw blk %d\n", rc);

		goto blk_init_error;

	}



	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,

		c->hw.blk_off + c->hw.length, c->hw.xin_id);



	return c;



blk_init_error:

	kzfree(c);



	return ERR_PTR(rc);

}



void sde_hw_dsc_destroy(struct sde_hw_dsc *dsc)

{

	if (dsc)

		sde_hw_blk_destroy(&dsc->base);

	kfree(dsc);

}