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Commit 64c804e9 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Support SDM450 poweroff sequence with PMI632"

parents be566880 f0178c93

Documentation/devicetree/bindings/input/qpnp-power-on.txt

+28 −1
Original line number Diff line number Diff line
@@ -84,7 +84,34 @@ Optional properties: 
				case.

- qcom,kpdpwr-sw-debounce	Boolean property to enable the debounce logic

				on the KPDPWR_N rising edge.



- qcom,resin-pon-reset		Boolean property which indicates that resin

				needs to be configured during reset in addition

				to the primary PON device that is configured

				for system reset through qcom,system-reset

				property.

- qcom,resin-warm-reset-type 	Poweroff type required to be configured on

				RESIN reset control register when the system

				goes for warm reset. If this property is not

				specified, then the default type, warm reset

				will be configured to RESIN reset control

				register. This property is effective only if

				qcom,resin-pon-reset is defined.

- qcom,resin-hard-reset-type 	Same description as qcom,resin-warm-reset-type

				but this applies for the system hard reset case.

- qcom,resin-shutdown-type   	Same description as qcom,resin-warm-reset-type

				but this applies for the system shutdown case.

- qcom,resin-shutdown-disable	Boolean property to disable RESIN POFF

				trigger during system shutdown case.

				This property is effective only if

				qcom,resin-pon-reset is defined.

- qcom,resin-hard-reset-disable	Boolean property to disable RESIN POFF

	                        trigger during system hard reset case.

				This property is effective only if

				qcom,resin-pon-reset is defined.

- qcom,ps-hold-shutdown-disable	Boolean property to disable PS_HOLD POFF

				trigger during system shutdown case.

- qcom,ps-hold-hard-reset-disable	Boolean property to disable PS_HOLD

				POFF trigger during system hard reset case.



All the below properties are in the sub-node section (properties of the child

node).

arch/arm64/boot/dts/qcom/sdm450-pmi632.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -21,3 +21,8 @@ 
&pm8953_typec {

	status = "disabled";

};



&pmi632_pon {

	qcom,ps-hold-hard-reset-disable;

	qcom,ps-hold-shutdown-disable;

};

drivers/input/misc/qpnp-power-on.c

+166 −2
Original line number Diff line number Diff line
@@ -212,6 +212,9 @@ struct qpnp_pon { 
	int			warm_reset_poff_type;

	int			hard_reset_poff_type;

	int			shutdown_poff_type;

	int			resin_warm_reset_type;

	int			resin_hard_reset_type;

	int			resin_shutdown_type;

	u16			base;

	u8			subtype;

	u8			pon_ver;
@@ -219,7 +222,12 @@ struct qpnp_pon { 
	u8			warm_reset_reason2;

	bool			is_spon;

	bool			store_hard_reset_reason;

	bool			resin_hard_reset_disable;

	bool			resin_shutdown_disable;

	bool			ps_hold_hard_reset_disable;

	bool			ps_hold_shutdown_disable;

	bool			kpdpwr_dbc_enable;

	bool			resin_pon_reset;

	ktime_t			kpdpwr_last_release_time;

};
@@ -478,6 +486,7 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon, 
		enum pon_power_off_type type)

{

	int rc;

	bool disable = false;

	u16 rst_en_reg;



	if (pon->pon_ver == QPNP_PON_GEN1_V1)
@@ -497,10 +506,12 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon, 
	case PON_POWER_OFF_HARD_RESET:

		if (pon->hard_reset_poff_type != -EINVAL)

			type = pon->hard_reset_poff_type;

		disable = pon->ps_hold_hard_reset_disable;

		break;

	case PON_POWER_OFF_SHUTDOWN:

		if (pon->shutdown_poff_type != -EINVAL)

			type = pon->shutdown_poff_type;

		disable = pon->ps_hold_shutdown_disable;

		break;

	default:

		break;
@@ -512,6 +523,13 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon, 
			"Unable to write to addr=%hx, rc(%d)\n",

			rst_en_reg, rc);



	/*

	 * Check if ps-hold power off configuration needs to be disabled.

	 * If yes, then return without configuring.

	 */

	if (disable)

		return rc;



	/*

	 * We need 10 sleep clock cycles here. But since the clock is

	 * internally generated, we need to add 50% tolerance to be
@@ -533,7 +551,80 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon, 
			"Unable to write to addr=%hx, rc(%d)\n",

			rst_en_reg, rc);



	dev_dbg(&pon->pdev->dev, "power off type = 0x%02X\n", type);

	dev_dbg(&pon->pdev->dev, "ps_hold power off type = 0x%02X\n", type);

	return rc;

}



static int qpnp_resin_pon_reset_config(struct qpnp_pon *pon,

		enum pon_power_off_type type)

{

	int rc;

	bool disable = false;

	u16 rst_en_reg;



	if (pon->pon_ver == QPNP_PON_GEN1_V1)

		rst_en_reg = QPNP_PON_RESIN_S2_CNTL(pon);

	else

		rst_en_reg = QPNP_PON_RESIN_S2_CNTL2(pon);



	/*

	 * Based on the poweroff type set for a PON device through device tree

	 * change the type being configured into PON_RESIN_S2_CTL.

	 */

	switch (type) {

	case PON_POWER_OFF_WARM_RESET:

		if (pon->resin_warm_reset_type != -EINVAL)

			type = pon->resin_warm_reset_type;

		break;

	case PON_POWER_OFF_HARD_RESET:

		if (pon->resin_hard_reset_type != -EINVAL)

			type = pon->resin_hard_reset_type;

		disable = pon->resin_hard_reset_disable;

		break;

	case PON_POWER_OFF_SHUTDOWN:

		if (pon->resin_shutdown_type != -EINVAL)

			type = pon->resin_shutdown_type;

		disable = pon->resin_shutdown_disable;

		break;

	default:

		break;

	}



	rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_S2_CNTL_EN, 0);

	if (rc)

		dev_err(&pon->pdev->dev,

			"Unable to write to addr=%hx, rc(%d)\n",

			rst_en_reg, rc);



	/*

	 * Check if resin power off configuration needs to be disabled.

	 * If yes, then return without configuring.

	 */

	if (disable)

		return rc;



	/*

	 * We need 10 sleep clock cycles here. But since the clock is

	 * internally generated, we need to add 50% tolerance to be

	 * conservative.

	 */

	udelay(500);



	rc = qpnp_pon_masked_write(pon, QPNP_PON_RESIN_S2_CNTL(pon),

				   QPNP_PON_S2_CNTL_TYPE_MASK, type);

	if (rc)

		dev_err(&pon->pdev->dev,

			"Unable to write to addr=%x, rc(%d)\n",

				QPNP_PON_RESIN_S2_CNTL(pon), rc);



	rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_S2_CNTL_EN,

						    QPNP_PON_S2_CNTL_EN);

	if (rc)

		dev_err(&pon->pdev->dev,

			"Unable to write to addr=%hx, rc(%d)\n",

			rst_en_reg, rc);



	dev_dbg(&pon->pdev->dev, "resin power off type = 0x%02X\n", type);

	return rc;

}
@@ -588,6 +679,15 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type) 
				rc);

			goto out;

		}

		if (pon->resin_pon_reset) {

			rc = qpnp_resin_pon_reset_config(pon, type);

			if (rc) {

				dev_err(&pon->pdev->dev,

					"Error configuring secondary PON resin rc: %d\n",

					rc);

				goto out;

			}

		}

	}

	/* Set ship mode here if it has been requested */

	if (!!pon_ship_mode_en) {
@@ -2337,6 +2437,69 @@ static int qpnp_pon_probe(struct platform_device *pdev) 
		pon->shutdown_poff_type = -EINVAL;

	}



	pon->ps_hold_hard_reset_disable =

					of_property_read_bool(pdev->dev.of_node,

					"qcom,ps-hold-hard-reset-disable");

	pon->ps_hold_shutdown_disable = of_property_read_bool(pdev->dev.of_node,

					"qcom,ps-hold-shutdown-disable");





	pon->resin_pon_reset = of_property_read_bool(pdev->dev.of_node,

					"qcom,resin-pon-reset");



	rc = of_property_read_u32(pon->pdev->dev.of_node,

				"qcom,resin-warm-reset-type",

				&pon->resin_warm_reset_type);

	if (rc) {

		if (rc != -EINVAL) {

			dev_err(&pdev->dev, "Unable to read resin warm reset poweroff type rc: %d\n",

				rc);

			goto err_out;

		}

		pon->resin_warm_reset_type = -EINVAL;

	} else if (pon->resin_warm_reset_type <= PON_POWER_OFF_RESERVED ||

			pon->resin_warm_reset_type >= PON_POWER_OFF_MAX_TYPE) {

		dev_err(&pdev->dev, "Invalid resin-warm-reset-type\n");

		pon->resin_warm_reset_type = -EINVAL;

	}



	rc = of_property_read_u32(pon->pdev->dev.of_node,

				"qcom,resin-hard-reset-type",

				&pon->resin_hard_reset_type);

	if (rc) {

		if (rc != -EINVAL) {

			dev_err(&pdev->dev, "Unable to read resin hard reset poweroff type rc: %d\n",

				rc);

			goto err_out;

		}

		pon->resin_hard_reset_type = -EINVAL;

	} else if (pon->resin_hard_reset_type <= PON_POWER_OFF_RESERVED ||

			pon->resin_hard_reset_type >= PON_POWER_OFF_MAX_TYPE) {

		dev_err(&pdev->dev, "Invalid resin-hard-reset-type\n");

		pon->resin_hard_reset_type = -EINVAL;

	}



	rc = of_property_read_u32(pon->pdev->dev.of_node,

				"qcom,resin-shutdown-type",

				&pon->resin_shutdown_type);

	if (rc) {

		if (rc != -EINVAL) {

			dev_err(&pdev->dev, "Unable to read resin shutdown poweroff type rc: %d\n",

				rc);

			goto err_out;

		}

		pon->resin_shutdown_type = -EINVAL;

	} else if (pon->resin_shutdown_type <= PON_POWER_OFF_RESERVED ||

			pon->resin_shutdown_type >= PON_POWER_OFF_MAX_TYPE) {

		dev_err(&pdev->dev, "Invalid resin-shutdown-type\n");

		pon->resin_shutdown_type = -EINVAL;

	}



	pon->resin_hard_reset_disable = of_property_read_bool(pdev->dev.of_node,

					"qcom,resin-hard-reset-disable");

	pon->resin_shutdown_disable = of_property_read_bool(pdev->dev.of_node,

					"qcom,resin-shutdown-disable");



	rc = device_create_file(&pdev->dev, &dev_attr_debounce_us);

	if (rc) {

		dev_err(&pdev->dev, "sys file creation failed rc: %d\n", rc);
@@ -2365,6 +2528,7 @@ static int qpnp_pon_probe(struct platform_device *pdev) 
	return 0;



err_out:

	if (sys_reset)

		sys_reset_dev = NULL;

	return rc;

}