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Commit 642e5167 authored by Jyri Sarha's avatar Jyri Sarha
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drm/tilcdc: Clean up LCDC functional clock rate setting code 



Clean up LCDC functional clock rate setting code.

The LCDC functional clock is set by two functions: mode_set_nofb() and
cpufreq_transition().

When tilcdc_crtc_mode_set_nofb() is called in atomic commit phase the
drm atomic helpers have taken all the necessary drm locks and turned
off the crtc, while tilcdc_commit() is keeping LCDC powered on. For
mode_set_nofb() just a simple clock setting function without any
locking or power management code is enough. The new tilcdc_crtc_set_clk()
is implemented for that purpose.

cpufreq_transition() on the other hand is called from outside DRM and
it needs to take the necessary locks and turn off the CRTC while
keeping the LCDC powered. The reimplemented tilcdc_crtc_update_clk()
is for that purpose and it uses the new tilcdc_crtc_set_clk() to
actually set the clock.

Signed-off-by: default avatarJyri Sarha <jsarha@ti.com>
Reviewed-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent a6b7ebaa

drivers/gpu/drm/tilcdc/tilcdc_crtc.c

+45 −32
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ struct tilcdc_crtc { 
	bool frame_done;

	spinlock_t irq_lock;



	unsigned int lcd_fck_rate;



	ktime_t last_vblank;



	struct drm_framebuffer *curr_fb;
@@ -304,6 +306,37 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 
	return true;

}



static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct tilcdc_drm_private *priv = dev->dev_private;

	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);

	const unsigned clkdiv = 2; /* using a fixed divider of 2 */

	int ret;



	/* mode.clock is in KHz, set_rate wants parameter in Hz */

	ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);

	if (ret < 0) {

		dev_err(dev->dev, "failed to set display clock rate to: %d\n",

			crtc->mode.clock);

		return;

	}



	tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk);



	DBG("lcd_clk=%u, mode clock=%d, div=%u",

	    tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);



	/* Configure the LCD clock divisor. */

	tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |

		     LCDC_RASTER_MODE);



	if (priv->rev == 2)

		tilcdc_set(dev, LCDC_CLK_ENABLE_REG,

				LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |

				LCDC_V2_CORE_CLK_EN);

}



static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)

{

	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
@@ -466,7 +499,7 @@ static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 


	set_scanout(crtc, fb);



	tilcdc_crtc_update_clk(crtc);

	tilcdc_crtc_set_clk(crtc);



	crtc->hwmode = crtc->state->adjusted_mode;

}
@@ -635,42 +668,22 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 
{

	struct drm_device *dev = crtc->dev;

	struct tilcdc_drm_private *priv = dev->dev_private;

	unsigned long lcd_clk;

	const unsigned clkdiv = 2; /* using a fixed divider of 2 */

	int ret;

	struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);



	drm_modeset_lock_crtc(crtc, NULL);

	if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {

		if (tilcdc_crtc_is_on(crtc)) {

			pm_runtime_get_sync(dev->dev);



			tilcdc_crtc_disable(crtc);



	/* mode.clock is in KHz, set_rate wants parameter in Hz */

	ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);

	if (ret < 0) {

		dev_err(dev->dev, "failed to set display clock rate to: %d\n",

				crtc->mode.clock);

		goto out;

	}



	lcd_clk = clk_get_rate(priv->clk);

			tilcdc_crtc_set_clk(crtc);



	DBG("lcd_clk=%lu, mode clock=%d, div=%u",

		lcd_clk, crtc->mode.clock, clkdiv);



	/* Configure the LCD clock divisor. */

	tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |

			LCDC_RASTER_MODE);



	if (priv->rev == 2)

		tilcdc_set(dev, LCDC_CLK_ENABLE_REG,

				LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |

				LCDC_V2_CORE_CLK_EN);



	if (tilcdc_crtc_is_on(crtc))

			tilcdc_crtc_enable(crtc);



out:

			pm_runtime_put_sync(dev->dev);

		}

	}

	drm_modeset_unlock_crtc(crtc);

}



#define SYNC_LOST_COUNT_LIMIT 50

drivers/gpu/drm/tilcdc/tilcdc_drv.c

+2 −9
Original line number Diff line number Diff line
@@ -185,14 +185,8 @@ static int cpufreq_transition(struct notifier_block *nb, 
	struct tilcdc_drm_private *priv = container_of(nb,

			struct tilcdc_drm_private, freq_transition);



	if (val == CPUFREQ_POSTCHANGE) {

		if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {

			drm_modeset_lock_crtc(priv->crtc, NULL);

			priv->lcd_fck_rate = clk_get_rate(priv->clk);

	if (val == CPUFREQ_POSTCHANGE)

		tilcdc_crtc_update_clk(priv->crtc);

			drm_modeset_unlock_crtc(priv->crtc);

		}

	}



	return 0;

}
@@ -286,7 +280,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) 
	}



#ifdef CONFIG_CPU_FREQ

	priv->lcd_fck_rate = clk_get_rate(priv->clk);

	priv->freq_transition.notifier_call = cpufreq_transition;

	ret = cpufreq_register_notifier(&priv->freq_transition,

			CPUFREQ_TRANSITION_NOTIFIER);

drivers/gpu/drm/tilcdc/tilcdc_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -74,7 +74,6 @@ struct tilcdc_drm_private { 


#ifdef CONFIG_CPU_FREQ

	struct notifier_block freq_transition;

	unsigned int lcd_fck_rate;

#endif



	struct workqueue_struct *wq;