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Commit 6364691d authored by Sundara Vinayagam's avatar Sundara Vinayagam Committed by Gerrit - the friendly Code Review server
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power: qpnp-fg-gen3: Fix fuel-gen3 compilation issues 



Resolved compilation error related to 64 bit division on 32 bit.

Change-Id: Id44ab8c07c497f0d2b150b825710b911513f93b1
Signed-off-by: default avatarSundara Vinayagam <sundvi@codeaurora.org>
parent 93ab52c1

drivers/power/supply/qcom/qpnp-fg-gen3.c

+7 −7
Original line number Diff line number Diff line
@@ -1408,16 +1408,16 @@ static void fg_cap_learning_post_process(struct fg_chip *chip) 
			QNOVO_CL_SKEW_DECIPCT, chip->cl.final_cc_uah);

		chip->cl.final_cc_uah = chip->cl.final_cc_uah *

						(1000 + QNOVO_CL_SKEW_DECIPCT);

		do_div(chip->cl.final_cc_uah, 1000);

		div64_s64(chip->cl.final_cc_uah, 1000);

	}



	max_inc_val = chip->cl.learned_cc_uah

			* (1000 + chip->dt.cl_max_cap_inc);

	do_div(max_inc_val, 1000);

	div64_s64(max_inc_val, 1000);



	min_dec_val = chip->cl.learned_cc_uah

			* (1000 - chip->dt.cl_max_cap_dec);

	do_div(min_dec_val, 1000);

	div64_s64(min_dec_val, 1000);



	old_cap = chip->cl.learned_cc_uah;

	if (chip->cl.final_cc_uah > max_inc_val)
@@ -1431,7 +1431,7 @@ static void fg_cap_learning_post_process(struct fg_chip *chip) 
	if (chip->dt.cl_max_cap_limit) {

		max_inc_val = (int64_t)chip->cl.nom_cap_uah * (1000 +

				chip->dt.cl_max_cap_limit);

		do_div(max_inc_val, 1000);

		div64_s64(max_inc_val, 1000);

		if (chip->cl.final_cc_uah > max_inc_val) {

			fg_dbg(chip, FG_CAP_LEARN, "learning capacity %lld goes above max limit %lld\n",

				chip->cl.final_cc_uah, max_inc_val);
@@ -1442,7 +1442,7 @@ static void fg_cap_learning_post_process(struct fg_chip *chip) 
	if (chip->dt.cl_min_cap_limit) {

		min_dec_val = (int64_t)chip->cl.nom_cap_uah * (1000 -

				chip->dt.cl_min_cap_limit);

		do_div(min_dec_val, 1000);

		div64_s64(min_dec_val, 1000);

		if (chip->cl.final_cc_uah < min_dec_val) {

			fg_dbg(chip, FG_CAP_LEARN, "learning capacity %lld goes below min limit %lld\n",

				chip->cl.final_cc_uah, min_dec_val);
@@ -1946,7 +1946,7 @@ static int fg_rconn_config(struct fg_chip *chip) 
	}



	val *= scaling_factor;

	do_div(val, 1000);

	div64_s64(val, 1000);

	rc = fg_sram_write(chip, ESR_RSLOW_CHG_WORD,

			ESR_RSLOW_CHG_OFFSET, (u8 *)&val, 1, FG_IMA_DEFAULT);

	if (rc < 0) {
@@ -1963,7 +1963,7 @@ static int fg_rconn_config(struct fg_chip *chip) 
	}



	val *= scaling_factor;

	do_div(val, 1000);

	div64_s64(val, 1000);

	rc = fg_sram_write(chip, ESR_RSLOW_DISCHG_WORD,

			ESR_RSLOW_DISCHG_OFFSET, (u8 *)&val, 1, FG_IMA_DEFAULT);

	if (rc < 0) {