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Commit 632818fb authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Gerrit - the friendly Code Review server
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clk: msm: Add support for 2GHz for a53ss_c1_pll 



CPU clock requires to support 2GHz, so a53ss_c1_pll
PLL which drives this clock needs to have support for
the same.

Change-Id: I0e44c8eb46c3b2f3287f7763d8ce90310affd0e9
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
parent 3440aa4e

drivers/clk/msm/clock-gcc-8952.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -274,6 +274,7 @@ static struct pll_freq_tbl apcs_c1_pll_freq[] = { 
	F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),

	F_APCS_PLL(2016000000, 105, 0x0, 0x1, 0x0, 0x0, 0x0),

};

};





static struct pll_clk a53ss_c1_pll = {

static struct pll_clk a53ss_c1_pll = {
@@ -304,7 +305,7 @@ static struct pll_clk a53ss_c1_pll = { 
		.vdd_class = &vdd_hf_pll,

		.vdd_class = &vdd_hf_pll,

		.fmax = (unsigned long [VDD_HF_PLL_NUM]) {

		.fmax = (unsigned long [VDD_HF_PLL_NUM]) {

			[VDD_HF_PLL_SVS] = 1000000000,

			[VDD_HF_PLL_SVS] = 1000000000,

			[VDD_HF_PLL_NOM] = 2000000000,

			[VDD_HF_PLL_NOM] = 2020000000,

		},

		},

		.num_fmax = VDD_HF_PLL_NUM,

		.num_fmax = VDD_HF_PLL_NUM,

		CLK_INIT(a53ss_c1_pll.c),

		CLK_INIT(a53ss_c1_pll.c),