Loading drivers/platform/msm/ep_pcie/ep_pcie_com.h +1 −1 Original line number Diff line number Diff line Loading @@ -359,7 +359,7 @@ struct ep_pcie_dev_t { ulong global_irq_counter; bool dump_conf; bool config_mmio_init; bool enumerated; enum ep_pcie_link_status link_status; bool perst_deast; Loading drivers/platform/msm/ep_pcie/ep_pcie_core.c +9 −0 Original line number Diff line number Diff line Loading @@ -503,6 +503,13 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) "Initial version of MMIO is:0x%x\n", readl_relaxed(dev->mmio + PCIE20_MHIVER)); if (dev->config_mmio_init) { EP_PCIE_DBG(dev, "PCIe V%d: MMIO already initialized, return\n", dev->rev); return; } ep_pcie_write_reg(dev->mmio, PCIE20_MHICFG, 0x02800880); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_EXECENV, 0x2); ep_pcie_write_reg(dev->mmio, PCIE20_MHICTRL, 0x0); Loading @@ -511,6 +518,8 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_LOWER, 0x2); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_UPPER, 0x1); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_INTVEC, 0xffffffff); dev->config_mmio_init = true; } static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) Loading Loading
drivers/platform/msm/ep_pcie/ep_pcie_com.h +1 −1 Original line number Diff line number Diff line Loading @@ -359,7 +359,7 @@ struct ep_pcie_dev_t { ulong global_irq_counter; bool dump_conf; bool config_mmio_init; bool enumerated; enum ep_pcie_link_status link_status; bool perst_deast; Loading
drivers/platform/msm/ep_pcie/ep_pcie_core.c +9 −0 Original line number Diff line number Diff line Loading @@ -503,6 +503,13 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) "Initial version of MMIO is:0x%x\n", readl_relaxed(dev->mmio + PCIE20_MHIVER)); if (dev->config_mmio_init) { EP_PCIE_DBG(dev, "PCIe V%d: MMIO already initialized, return\n", dev->rev); return; } ep_pcie_write_reg(dev->mmio, PCIE20_MHICFG, 0x02800880); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_EXECENV, 0x2); ep_pcie_write_reg(dev->mmio, PCIE20_MHICTRL, 0x0); Loading @@ -511,6 +518,8 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_LOWER, 0x2); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_UPPER, 0x1); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_INTVEC, 0xffffffff); dev->config_mmio_init = true; } static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) Loading