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Commit 62e4d357 authored by Rob Herring's avatar Rob Herring Committed by Russell King
Browse files

ARM: 7609/1: disable errata work-arounds which access secure registers 



In order to support secure and non-secure platforms in multi-platform
kernels, errata work-arounds that access secure only registers need to
be disabled. Make all the errata options that fit in this category
depend on !CONFIG_ARCH_MULTIPLATFORM.

This will effectively remove the errata options as platforms are
converted over to multi-platform.

Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 74ddcdb8

arch/arm/Kconfig

+6 −0
Original line number Original line Diff line number Diff line
@@ -1230,6 +1230,7 @@ config ARM_ERRATA_430973 
config ARM_ERRATA_458693

config ARM_ERRATA_458693

	bool "ARM errata: Processor deadlock when a false hazard is created"

	bool "ARM errata: Processor deadlock when a false hazard is created"

	depends on CPU_V7

	depends on CPU_V7

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)

	  This option enables the workaround for the 458693 Cortex-A8 (r2p0)

	  erratum. For very specific sequences of memory operations, it is

	  erratum. For very specific sequences of memory operations, it is
@@ -1243,6 +1244,7 @@ config ARM_ERRATA_458693 
config ARM_ERRATA_460075

config ARM_ERRATA_460075

	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"

	bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"

	depends on CPU_V7

	depends on CPU_V7

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)

	  This option enables the workaround for the 460075 Cortex-A8 (r2p0)

	  erratum. Any asynchronous access to the L2 cache may encounter a

	  erratum. Any asynchronous access to the L2 cache may encounter a
@@ -1255,6 +1257,7 @@ config ARM_ERRATA_460075 
config ARM_ERRATA_742230

config ARM_ERRATA_742230

	bool "ARM errata: DMB operation may be faulty"

	bool "ARM errata: DMB operation may be faulty"

	depends on CPU_V7 && SMP

	depends on CPU_V7 && SMP

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 742230 Cortex-A9

	  This option enables the workaround for the 742230 Cortex-A9

	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction

	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
@@ -1267,6 +1270,7 @@ config ARM_ERRATA_742230 
config ARM_ERRATA_742231

config ARM_ERRATA_742231

	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"

	bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"

	depends on CPU_V7 && SMP

	depends on CPU_V7 && SMP

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 742231 Cortex-A9

	  This option enables the workaround for the 742231 Cortex-A9

	  (r2p0..r2p2) erratum. Under certain conditions, specific to the

	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
@@ -1317,6 +1321,7 @@ config PL310_ERRATA_727915 
config ARM_ERRATA_743622

config ARM_ERRATA_743622

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	depends on CPU_V7

	depends on CPU_V7

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 743622 Cortex-A9

	  This option enables the workaround for the 743622 Cortex-A9

	  (r2p*) erratum. Under very rare conditions, a faulty

	  (r2p*) erratum. Under very rare conditions, a faulty
@@ -1330,6 +1335,7 @@ config ARM_ERRATA_743622 
config ARM_ERRATA_751472

config ARM_ERRATA_751472

	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"

	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"

	depends on CPU_V7

	depends on CPU_V7

	depends on !ARCH_MULTIPLATFORM

	help

	help

	  This option enables the workaround for the 751472 Cortex-A9 (prior

	  This option enables the workaround for the 751472 Cortex-A9 (prior

	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the

	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the

arch/arm/mach-vexpress/Kconfig

+0 −1
Original line number Original line Diff line number Diff line
@@ -42,7 +42,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA 
	bool "Enable A5 and A9 only errata work-arounds"

	bool "Enable A5 and A9 only errata work-arounds"

	default y

	default y

	select ARM_ERRATA_720789

	select ARM_ERRATA_720789

	select ARM_ERRATA_751472

	select PL310_ERRATA_753970 if CACHE_PL310

	select PL310_ERRATA_753970 if CACHE_PL310

	help

	help

	  Provides common dependencies for Versatile Express platforms

	  Provides common dependencies for Versatile Express platforms

arch/arm/mm/proc-v7.S

+2 −1
Original line number Original line Diff line number Diff line
@@ -245,7 +245,8 @@ __v7_setup: 
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number

	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number

	teq	r0, r10

	teq	r0, r10

	bne	2f

	bne	2f

#ifdef CONFIG_ARM_ERRATA_430973

#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)



	teq	r5, #0x00100000			@ only present in r1p*

	teq	r5, #0x00100000			@ only present in r1p*

	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register

	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register

	orreq	r10, r10, #(1 << 6)		@ set IBE to 1

	orreq	r10, r10, #(1 << 6)		@ set IBE to 1