Blackfin: BF51x: add PTP MMR defines

#define bfin_read_EMAC_TXC_ABORT()		bfin_read32(EMAC_TXC_ABORT)

#define bfin_write_EMAC_TXC_ABORT(val)		bfin_write32(EMAC_TXC_ABORT, val)

#define bfin_read_EMAC_PTP_CTL()                bfin_read16(EMAC_PTP_CTL)

#define bfin_write_EMAC_PTP_CTL(val)            bfin_write16(EMAC_PTP_CTL, val)

#define bfin_read_EMAC_PTP_IE()                 bfin_read16(EMAC_PTP_IE)

#define bfin_write_EMAC_PTP_IE(val)             bfin_write16(EMAC_PTP_IE, val)

#define bfin_read_EMAC_PTP_ISTAT()              bfin_read16(EMAC_PTP_ISTAT)

#define bfin_write_EMAC_PTP_ISTAT(val)          bfin_write16(EMAC_PTP_ISTAT, val)

#define bfin_read_EMAC_PTP_FOFF()               bfin_read32(EMAC_PTP_FOFF)

#define bfin_write_EMAC_PTP_FOFF(val)           bfin_write32(EMAC_PTP_FOFF, val)

#define bfin_read_EMAC_PTP_FV1()                bfin_read32(EMAC_PTP_FV1)

#define bfin_write_EMAC_PTP_FV1(val)            bfin_write32(EMAC_PTP_FV1, val)

#define bfin_read_EMAC_PTP_FV2()                bfin_read32(EMAC_PTP_FV2)

#define bfin_write_EMAC_PTP_FV2(val)            bfin_write32(EMAC_PTP_FV2, val)

#define bfin_read_EMAC_PTP_FV3()                bfin_read32(EMAC_PTP_FV3)

#define bfin_write_EMAC_PTP_FV3(val)            bfin_write32(EMAC_PTP_FV3, val)

#define bfin_read_EMAC_PTP_ADDEND()             bfin_read32(EMAC_PTP_ADDEND)

#define bfin_write_EMAC_PTP_ADDEND(val)         bfin_write32(EMAC_PTP_ADDEND, val)

#define bfin_read_EMAC_PTP_ACCR()               bfin_read32(EMAC_PTP_ACCR)

#define bfin_write_EMAC_PTP_ACCR(val)           bfin_write32(EMAC_PTP_ACCR, val)

#define bfin_read_EMAC_PTP_OFFSET()             bfin_read32(EMAC_PTP_OFFSET)

#define bfin_write_EMAC_PTP_OFFSET(val)         bfin_write32(EMAC_PTP_OFFSET, val)

#define bfin_read_EMAC_PTP_TIMELO()             bfin_read32(EMAC_PTP_TIMELO)

#define bfin_write_EMAC_PTP_TIMELO(val)         bfin_write32(EMAC_PTP_TIMELO, val)

#define bfin_read_EMAC_PTP_TIMEHI()             bfin_read32(EMAC_PTP_TIMEHI)

#define bfin_write_EMAC_PTP_TIMEHI(val)         bfin_write32(EMAC_PTP_TIMEHI, val)

#define bfin_read_EMAC_PTP_RXSNAPLO()           bfin_read32(EMAC_PTP_RXSNAPLO)

#define bfin_read_EMAC_PTP_RXSNAPHI()           bfin_read32(EMAC_PTP_RXSNAPHI)

#define bfin_read_EMAC_PTP_TXSNAPLO()           bfin_read32(EMAC_PTP_TXSNAPLO)

#define bfin_read_EMAC_PTP_TXSNAPHI()           bfin_read32(EMAC_PTP_TXSNAPHI)

#define bfin_read_EMAC_PTP_ALARMLO()            bfin_read32(EMAC_PTP_ALARMLO)

#define bfin_write_EMAC_PTP_ALARMLO(val)        bfin_write32(EMAC_PTP_ALARMLO, val)

#define bfin_read_EMAC_PTP_ALARMHI()            bfin_read32(EMAC_PTP_ALARMHI)

#define bfin_write_EMAC_PTP_ALARMHI(val)        bfin_write32(EMAC_PTP_ALARMHI, val)

#define bfin_read_EMAC_PTP_ID_OFF()             bfin_read16(EMAC_PTP_ID_OFF)

#define bfin_write_EMAC_PTP_ID_OFF(val)         bfin_write16(EMAC_PTP_ID_OFF, val)

#define bfin_read_EMAC_PTP_ID_SNAP()            bfin_read32(EMAC_PTP_ID_SNAP)

#define bfin_write_EMAC_PTP_ID_SNAP(val)        bfin_write32(EMAC_PTP_ID_SNAP, val)

#define bfin_read_EMAC_PTP_PPS_STARTHI()        bfin_read32(EMAC_PTP_PPS_STARTHI)

#define bfin_write_EMAC_PTP_PPS_STARTHI(val)    bfin_write32(EMAC_PTP_PPS_STARTHI, val)

#define bfin_read_EMAC_PTP_PPS_PERIOD()         bfin_read32(EMAC_PTP_PPS_PERIOD)

#define bfin_write_EMAC_PTP_PPS_PERIOD(val)     bfin_write32(EMAC_PTP_PPS_PERIOD, val)

/* Removable Storage Interface Registers */

#define bfin_read_RSI_PWR_CTL()        bfin_read16(RSI_PWR_CONTROL)

#define                       RWR  0x1        /* Read Wait Request */

/* Bit masks for EMAC_PTP_CTL */

#define                    PTP_EN  0x1        /* Enable the PTP_TSYNC module */

#define                        TL  0x2        /* Timestamp lock control */

#define                      ASEN  0x10       /* Auxiliary snapshot control */

#define                     PPSEN  0x80       /* Pulse-per-second (PPS) control */

#define                     CKOEN  0x2000     /* Clock output control */

/* Bit masks for EMAC_PTP_IE */

#define                      ALIE  0x1        /* Alarm interrupt enable */

#define                     RXEIE  0x2        /* Receive event interrupt enable */

#define                     RXGIE  0x4        /* Receive general interrupt enable */

#define                      TXIE  0x8        /* Transmit interrupt enable */

#define                     RXOVE  0x10       /* Receive overrun error interrupt enable */

#define                     TXOVE  0x20       /* Transmit overrun error interrupt enable */

#define                      ASIE  0x40       /* Auxiliary snapshot interrupt enable */

/* Bit masks for EMAC_PTP_ISTAT */

#define                       ALS  0x1        /* Alarm status */

#define                      RXEL  0x2        /* Receive event interrupt status */

#define                      RXGL  0x4        /* Receive general interrupt status */

#define                      TXTL  0x8        /* Transmit snapshot status */

#define                      RXOV  0x10       /* Receive snapshot overrun status */

#define                      TXOV  0x20       /* Transmit snapshot overrun status */

#define                       ASL  0x40       /* Auxiliary snapshot interrupt status */

#endif /* _DEF_BF518_H */