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Commit 6197349b authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915: Abstract PPGTT enabling 



Since we've already set up a nice vtable to abstract other PPGTT
functions, also abstract the actual register programming to enable
things.

This function will probably need to change a bit as we implement real
processes.

v2: Resolve conflicts due to patch series reordering.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3ed124b2

drivers/gpu/drm/i915/i915_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -927,7 +927,8 @@ int i915_reset(struct drm_device *dev) 
			ring->init(ring);



		i915_gem_context_init(dev);

		i915_gem_init_ppgtt(dev);

		if (dev_priv->mm.aliasing_ppgtt)

			dev_priv->mm.aliasing_ppgtt->enable(dev);



		/*

		 * It would make sense to re-init all the other hw state, at

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -449,6 +449,7 @@ struct i915_hw_ppgtt { 
			       struct sg_table *st,

			       unsigned int pg_start,

			       enum i915_cache_level cache_level);

	void (*enable)(struct drm_device *dev);

	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);

};
@@ -1642,7 +1643,6 @@ int __must_check i915_gem_init(struct drm_device *dev); 
int __must_check i915_gem_init_hw(struct drm_device *dev);

void i915_gem_l3_remap(struct drm_device *dev);

void i915_gem_init_swizzling(struct drm_device *dev);

void i915_gem_init_ppgtt(struct drm_device *dev);

void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

int __must_check i915_gpu_idle(struct drm_device *dev);

int __must_check i915_gem_idle(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+2 −1
Original line number Diff line number Diff line
@@ -4029,7 +4029,8 @@ i915_gem_init_hw(struct drm_device *dev) 
	 * contexts before PPGTT.

	 */

	i915_gem_context_init(dev);

	i915_gem_init_ppgtt(dev);

	if (dev_priv->mm.aliasing_ppgtt)

		dev_priv->mm.aliasing_ppgtt->enable(dev);



	return 0;

}

drivers/gpu/drm/i915/i915_gem_gtt.c

+56 −58
Original line number Diff line number Diff line
@@ -75,6 +75,61 @@ static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, 
	return pte;

}



static void gen6_ppgtt_enable(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	uint32_t pd_offset;

	struct intel_ring_buffer *ring;

	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

	gen6_gtt_pte_t __iomem *pd_addr;

	uint32_t pd_entry;

	int i;



	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +

		ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);

	for (i = 0; i < ppgtt->num_pd_entries; i++) {

		dma_addr_t pt_addr;



		pt_addr = ppgtt->pt_dma_addr[i];

		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);

		pd_entry |= GEN6_PDE_VALID;



		writel(pd_entry, pd_addr + i);

	}

	readl(pd_addr);



	pd_offset = ppgtt->pd_offset;

	pd_offset /= 64; /* in cachelines, */

	pd_offset <<= 16;



	if (INTEL_INFO(dev)->gen == 6) {

		uint32_t ecochk, gab_ctl, ecobits;



		ecobits = I915_READ(GAC_ECO_BITS);

		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);



		gab_ctl = I915_READ(GAB_CTL);

		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);



		ecochk = I915_READ(GAM_ECOCHK);

		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |

				       ECOCHK_PPGTT_CACHE64B);

		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

	} else if (INTEL_INFO(dev)->gen >= 7) {

		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);

		/* GFX_MODE is per-ring on gen7+ */

	}



	for_each_ring(ring, dev_priv, i) {

		if (INTEL_INFO(dev)->gen >= 7)

			I915_WRITE(RING_MODE_GEN7(ring),

				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));



		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);

		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);

	}

}



/* PPGTT support for Sandybdrige/Gen6 and later */

static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,

				   unsigned first_entry,
@@ -168,6 +223,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) 
		gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;



	ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;

	ppgtt->enable = gen6_ppgtt_enable;

	ppgtt->clear_range = gen6_ppgtt_clear_range;

	ppgtt->insert_entries = gen6_ppgtt_insert_entries;

	ppgtt->cleanup = gen6_ppgtt_cleanup;
@@ -279,64 +335,6 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 
			   obj->base.size >> PAGE_SHIFT);

}



void i915_gem_init_ppgtt(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	uint32_t pd_offset;

	struct intel_ring_buffer *ring;

	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

	gen6_gtt_pte_t __iomem *pd_addr;

	uint32_t pd_entry;

	int i;



	if (!dev_priv->mm.aliasing_ppgtt)

		return;



	pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +

		ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);

	for (i = 0; i < ppgtt->num_pd_entries; i++) {

		dma_addr_t pt_addr;



		pt_addr = ppgtt->pt_dma_addr[i];

		pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);

		pd_entry |= GEN6_PDE_VALID;



		writel(pd_entry, pd_addr + i);

	}

	readl(pd_addr);



	pd_offset = ppgtt->pd_offset;

	pd_offset /= 64; /* in cachelines, */

	pd_offset <<= 16;



	if (INTEL_INFO(dev)->gen == 6) {

		uint32_t ecochk, gab_ctl, ecobits;



		ecobits = I915_READ(GAC_ECO_BITS);

		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);



		gab_ctl = I915_READ(GAB_CTL);

		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);



		ecochk = I915_READ(GAM_ECOCHK);

		I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |

				       ECOCHK_PPGTT_CACHE64B);

		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));

	} else if (INTEL_INFO(dev)->gen >= 7) {

		I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);

		/* GFX_MODE is per-ring on gen7+ */

	}



	for_each_ring(ring, dev_priv, i) {

		if (INTEL_INFO(dev)->gen >= 7)

			I915_WRITE(RING_MODE_GEN7(ring),

				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));



		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);

		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);

	}

}



extern int intel_iommu_gfx_mapped;

/* Certain Gen5 chipsets require require idling the GPU before

 * unmapping anything from the GTT when VT-d is enabled.