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Commit 60ecb1ef authored by Emilio López's avatar Emilio López Committed by Maxime Ripard
Browse files

ARM: sun7i: Add mod1 clock nodes 



This commit adds all the mod1 clocks available on A20 to its device
tree. This list was created by looking at the A20 user manual.

Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent e6495c86

arch/arm/boot/dts/sun7i-a20.dtsi

+46 −2
Original line number Diff line number Diff line
@@ -371,9 +371,9 @@ 
					<5>, <6>, <7>,

					<8>, <10>;

			clock-output-names = "apb0_codec", "apb0_spdif",

				"apb0_ac97", "apb0_iis0", "apb0_iis1",

				"apb0_ac97", "apb0_i2s0", "apb0_i2s1",

				"apb0_pio", "apb0_ir0", "apb0_ir1",

				"apb0_iis2", "apb0_keypad";

				"apb0_i2s2", "apb0_keypad";

		};



		apb1: clk@01c20058 {
@@ -523,6 +523,28 @@ 
			clock-output-names = "ir1";

		};



		i2s0_clk: clk@01c200b8 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod1-clk";

			reg = <0x01c200b8 0x4>;

			clocks = <&pll2 SUN4I_A10_PLL2_8X>,

				 <&pll2 SUN4I_A10_PLL2_4X>,

				 <&pll2 SUN4I_A10_PLL2_2X>,

				 <&pll2 SUN4I_A10_PLL2_1X>;

			clock-output-names = "i2s0";

		};



		ac97_clk: clk@01c200bc {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod1-clk";

			reg = <0x01c200bc 0x4>;

			clocks = <&pll2 SUN4I_A10_PLL2_8X>,

				 <&pll2 SUN4I_A10_PLL2_4X>,

				 <&pll2 SUN4I_A10_PLL2_2X>,

				 <&pll2 SUN4I_A10_PLL2_1X>;

			clock-output-names = "ac97";

		};



		spdif_clk: clk@01c200c0 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod1-clk";
@@ -560,6 +582,28 @@ 
			clock-output-names = "spi3";

		};



		i2s1_clk: clk@01c200d8 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod1-clk";

			reg = <0x01c200d8 0x4>;

			clocks = <&pll2 SUN4I_A10_PLL2_8X>,

				 <&pll2 SUN4I_A10_PLL2_4X>,

				 <&pll2 SUN4I_A10_PLL2_2X>,

				 <&pll2 SUN4I_A10_PLL2_1X>;

			clock-output-names = "i2s1";

		};



		i2s2_clk: clk@01c200dc {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-a10-mod1-clk";

			reg = <0x01c200dc 0x4>;

			clocks = <&pll2 SUN4I_A10_PLL2_8X>,

				 <&pll2 SUN4I_A10_PLL2_4X>,

				 <&pll2 SUN4I_A10_PLL2_2X>,

				 <&pll2 SUN4I_A10_PLL2_1X>;

			clock-output-names = "i2s2";

		};



		dram_gates: clk@01c20100 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-a10-dram-gates-clk";