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Commit 60de02fa authored by Deepak Katragadda's avatar Deepak Katragadda
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dt-bindings: clock: Update the GCC clock entries for MSMSKUNK 



Update the peripheral clock references on MSMSKUNK to match the
new frequency plan.

Change-Id: Ife8ebb201e9e6fa1af34c6358dff52c05950a948
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent ef9e9117

include/dt-bindings/clock/qcom,gcc-skunk.h

+161 −180
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#ifndef _DT_BINDINGS_CLK_MSM_GCC_SKUNK_H

#define _DT_BINDINGS_CLK_MSM_GCC_SKUNK_H



/* GCC clocks */

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0

#define GCC_AGGRE_UFS_CARD_AXI_CLK				1

#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
@@ -35,186 +36,166 @@ 
#define GCC_DDRSS_GPU_AXI_CLK					18

#define GCC_DISP_AHB_CLK					19

#define GCC_DISP_AXI_CLK					20

#define GCC_DISP_XO_CLK						21

#define GCC_GP1_CLK						22

#define GCC_GP1_CLK_SRC						23

#define GCC_GP2_CLK						24

#define GCC_GP2_CLK_SRC						25

#define GCC_GP3_CLK						26

#define GCC_GP3_CLK_SRC						27

#define GCC_GPU_CFG_AHB_CLK					28

#define GCC_GPU_MEMNOC_GFX_CLK					29

#define GCC_GPU_SNOC_DVM_GFX_CLK				30

#define GCC_MMSS_QM_AHB_CLK					31

#define GCC_MMSS_QM_CORE_CLK					32

#define GCC_MMSS_QM_CORE_CLK_SRC				33

#define GCC_PCIE_0_AUX_CLK					34

#define GCC_PCIE_0_AUX_CLK_SRC					35

#define GCC_PCIE_0_CFG_AHB_CLK					36

#define GCC_PCIE_0_CLKREF_CLK					37

#define GCC_PCIE_0_MSTR_AXI_CLK					38

#define GCC_PCIE_0_PIPE_CLK					39

#define GCC_PCIE_0_SLV_AXI_CLK					40

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				41

#define GCC_PCIE_1_AUX_CLK					42

#define GCC_PCIE_1_AUX_CLK_SRC					43

#define GCC_PCIE_1_CFG_AHB_CLK					44

#define GCC_PCIE_1_CLKREF_CLK					45

#define GCC_PCIE_1_MSTR_AXI_CLK					46

#define GCC_PCIE_1_PIPE_CLK					47

#define GCC_PCIE_1_SLV_AXI_CLK					48

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				49

#define GCC_PCIE_PHY_AUX_CLK					50

#define GCC_PCIE_PHY_REFGEN_CLK					51

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				52

#define GCC_PDM2_CLK						53

#define GCC_PDM2_CLK_SRC					54

#define GCC_PDM_AHB_CLK						55

#define GCC_PDM_XO4_CLK						56

#define GCC_PRNG_AHB_CLK					57

#define GCC_QMIP_CAMERA_AHB_CLK					58

#define GCC_QMIP_DISP_AHB_CLK					59

#define GCC_QMIP_VIDEO_AHB_CLK					60

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				61

#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC				62

#define GCC_QUPV3_WRAP0_CORE_CLK				63

#define GCC_QUPV3_WRAP0_S0_CLK					64

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				65

#define GCC_QUPV3_WRAP0_S1_CLK					66

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				67

#define GCC_QUPV3_WRAP0_S2_CLK					68

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				69

#define GCC_QUPV3_WRAP0_S3_CLK					70

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				71

#define GCC_QUPV3_WRAP0_S4_CLK					72

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				73

#define GCC_QUPV3_WRAP0_S5_CLK					74

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S6_CLK					76

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S7_CLK					78

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				79

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				80

#define GCC_QUPV3_WRAP1_CORE_CLK				81

#define GCC_QUPV3_WRAP1_S0_CLK					82

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				83

#define GCC_QUPV3_WRAP1_S1_CLK					84

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				85

#define GCC_QUPV3_WRAP1_S2_CLK					86

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				87

#define GCC_QUPV3_WRAP1_S3_CLK					88

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				89

#define GCC_QUPV3_WRAP1_S4_CLK					90

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S5_CLK					92

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S6_CLK					94

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S7_CLK					96

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				97

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				98

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				99

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				100

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				101

#define GCC_RX1_USB2_CLKREF_CLK					102

#define GCC_RX2_QLINK_CLKREF_CLK				103

#define GCC_RX3_MODEM_CLKREF_CLK				104

#define GCC_SDCC2_AHB_CLK					105

#define GCC_SDCC2_APPS_CLK					106

#define GCC_SDCC2_APPS_CLK_SRC					107

#define GCC_SDCC4_AHB_CLK					108

#define GCC_SDCC4_APPS_CLK					109

#define GCC_SDCC4_APPS_CLK_SRC					110

#define GCC_SYS_NOC_CPUSS_AHB_CLK				111

#define GCC_TSIF_AHB_CLK					112

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				113

#define GCC_TSIF_REF_CLK					114

#define GCC_TSIF_REF_CLK_SRC					115

#define GCC_UFS_CARD_AHB_CLK					116

#define GCC_UFS_CARD_AXI_CLK					117

#define GCC_UFS_CARD_AXI_CLK_SRC				118

#define GCC_UFS_CARD_CLKREF_CLK					119

#define GCC_UFS_CARD_ICE_CORE_CLK				120

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				121

#define GCC_UFS_CARD_PHY_AUX_CLK				122

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				123

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				124

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				125

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				126

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				127

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			128

#define GCC_UFS_MEM_CLKREF_CLK					129

#define GCC_UFS_PHY_AHB_CLK					130

#define GCC_UFS_PHY_AXI_CLK					131

#define GCC_UFS_PHY_AXI_CLK_SRC					132

#define GCC_UFS_PHY_ICE_CORE_CLK				133

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				134

#define GCC_UFS_PHY_PHY_AUX_CLK					135

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				136

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				137

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				138

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				139

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				140

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				141

#define GCC_USB30_PRIM_MASTER_CLK				142

#define GCC_USB30_PRIM_MASTER_CLK_SRC				143

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				144

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			145

#define GCC_USB30_PRIM_SLEEP_CLK				146

#define GCC_USB30_SEC_MASTER_CLK				147

#define GCC_USB30_SEC_MASTER_CLK_SRC				148

#define GCC_USB30_SEC_MOCK_UTMI_CLK				149

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				150

#define GCC_USB30_SEC_SLEEP_CLK					151

#define GCC_USB3_PRIM_CLKREF_CLK				152

#define GCC_USB3_PRIM_PHY_AUX_CLK				153

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				154

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				155

#define GCC_USB3_PRIM_PHY_PIPE_CLK				156

#define GCC_USB3_SEC_CLKREF_CLK					157

#define GCC_USB3_SEC_PHY_AUX_CLK				158

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				159

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				160

#define GCC_USB3_SEC_PHY_PIPE_CLK				161

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				162

#define GCC_VIDEO_AHB_CLK					163

#define GCC_VIDEO_AXI_CLK					164

#define GCC_VIDEO_XO_CLK					165

#define GPLL0							166

#define GPLL0_OUT_EVEN						167

#define GPLL0_OUT_MAIN						168

#define GPLL0_OUT_ODD						169

#define GPLL0_OUT_TEST						170

#define GPLL1							171

#define GPLL1_OUT_EVEN						172

#define GPLL1_OUT_MAIN						173

#define GPLL1_OUT_ODD						174

#define GPLL1_OUT_TEST						175

#define GPLL2							176

#define GPLL2_OUT_EVEN						177

#define GPLL2_OUT_MAIN						178

#define GPLL2_OUT_ODD						179

#define GPLL2_OUT_TEST						180

#define GPLL3							181

#define GPLL3_OUT_EVEN						182

#define GPLL3_OUT_MAIN						183

#define GPLL3_OUT_ODD						184

#define GPLL3_OUT_TEST						185

#define GPLL4							186

#define GPLL4_OUT_EVEN						187

#define GPLL4_OUT_MAIN						188

#define GPLL4_OUT_ODD						189

#define GPLL4_OUT_TEST						190

#define GPLL5							191

#define GPLL5_OUT_EVEN						192

#define GPLL5_OUT_MAIN						193

#define GPLL5_OUT_ODD						194

#define GPLL5_OUT_TEST						195

#define GPLL6							196

#define GPLL6_OUT_EVEN						197

#define GPLL6_OUT_MAIN						198

#define GPLL6_OUT_ODD						199

#define GPLL6_OUT_TEST						200

#define GCC_DISP_GPLL0_CLK_SRC					21

#define GCC_DISP_GPLL0_DIV_CLK_SRC				22

#define GCC_DISP_XO_CLK						23

#define GCC_GP1_CLK						24

#define GCC_GP1_CLK_SRC						25

#define GCC_GP2_CLK						26

#define GCC_GP2_CLK_SRC						27

#define GCC_GP3_CLK						28

#define GCC_GP3_CLK_SRC						29

#define GCC_GPU_CFG_AHB_CLK					30

#define GCC_GPU_GPLL0_CLK_SRC					31

#define GCC_GPU_GPLL0_DIV_CLK_SRC				32

#define GCC_GPU_MEMNOC_GFX_CLK					33

#define GCC_GPU_SNOC_DVM_GFX_CLK				34

#define GCC_MMSS_QM_AHB_CLK					35

#define GCC_MMSS_QM_CORE_CLK					36

#define GCC_MMSS_QM_CORE_CLK_SRC				37

#define GCC_MSS_AXIS2_CLK					38

#define GCC_MSS_CFG_AHB_CLK					39

#define GCC_MSS_GPLL0_DIV_CLK_SRC				40

#define GCC_MSS_MFAB_AXIS_CLK					41

#define GCC_MSS_Q6_MEMNOC_AXI_CLK				42

#define GCC_MSS_SNOC_AXI_CLK					43

#define GCC_PCIE_0_AUX_CLK					44

#define GCC_PCIE_0_AUX_CLK_SRC					45

#define GCC_PCIE_0_CFG_AHB_CLK					46

#define GCC_PCIE_0_CLKREF_CLK					47

#define GCC_PCIE_0_MSTR_AXI_CLK					48

#define GCC_PCIE_0_PIPE_CLK					49

#define GCC_PCIE_0_SLV_AXI_CLK					50

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				51

#define GCC_PCIE_1_AUX_CLK					52

#define GCC_PCIE_1_AUX_CLK_SRC					53

#define GCC_PCIE_1_CFG_AHB_CLK					54

#define GCC_PCIE_1_CLKREF_CLK					55

#define GCC_PCIE_1_MSTR_AXI_CLK					56

#define GCC_PCIE_1_PIPE_CLK					57

#define GCC_PCIE_1_SLV_AXI_CLK					58

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				59

#define GCC_PCIE_PHY_AUX_CLK					60

#define GCC_PCIE_PHY_REFGEN_CLK					61

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				62

#define GCC_PDM2_CLK						63

#define GCC_PDM2_CLK_SRC					64

#define GCC_PDM_AHB_CLK						65

#define GCC_PDM_XO4_CLK						66

#define GCC_PRNG_AHB_CLK					67

#define GCC_QMIP_CAMERA_AHB_CLK					68

#define GCC_QMIP_DISP_AHB_CLK					69

#define GCC_QMIP_VIDEO_AHB_CLK					70

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				71

#define GCC_QUPV3_WRAP0_CORE_2X_CLK_SRC				72

#define GCC_QUPV3_WRAP0_CORE_CLK				73

#define GCC_QUPV3_WRAP0_S0_CLK					74

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S1_CLK					76

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S2_CLK					78

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S3_CLK					80

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S4_CLK					82

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S5_CLK					84

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S6_CLK					86

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S7_CLK					88

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				89

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				90

#define GCC_QUPV3_WRAP1_CORE_CLK				91

#define GCC_QUPV3_WRAP1_S0_CLK					92

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S1_CLK					94

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S2_CLK					96

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S3_CLK					98

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S4_CLK					100

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S5_CLK					102

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S6_CLK					104

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S7_CLK					106

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				107

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				108

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				109

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				110

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				111

#define GCC_RX1_USB2_CLKREF_CLK					112

#define GCC_RX2_QLINK_CLKREF_CLK				113

#define GCC_RX3_MODEM_CLKREF_CLK				114

#define GCC_SDCC2_AHB_CLK					115

#define GCC_SDCC2_APPS_CLK					116

#define GCC_SDCC2_APPS_CLK_SRC					117

#define GCC_SDCC4_AHB_CLK					118

#define GCC_SDCC4_APPS_CLK					119

#define GCC_SDCC4_APPS_CLK_SRC					120

#define GCC_SYS_NOC_CPUSS_AHB_CLK				121

#define GCC_TSIF_AHB_CLK					122

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				123

#define GCC_TSIF_REF_CLK					124

#define GCC_TSIF_REF_CLK_SRC					125

#define GCC_UFS_CARD_AHB_CLK					126

#define GCC_UFS_CARD_AXI_CLK					127

#define GCC_UFS_CARD_AXI_CLK_SRC				128

#define GCC_UFS_CARD_CLKREF_CLK					129

#define GCC_UFS_CARD_ICE_CORE_CLK				130

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				131

#define GCC_UFS_CARD_PHY_AUX_CLK				132

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				133

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				134

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				135

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				136

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				137

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			138

#define GCC_UFS_MEM_CLKREF_CLK					139

#define GCC_UFS_PHY_AHB_CLK					140

#define GCC_UFS_PHY_AXI_CLK					141

#define GCC_UFS_PHY_AXI_CLK_SRC					142

#define GCC_UFS_PHY_ICE_CORE_CLK				143

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				144

#define GCC_UFS_PHY_PHY_AUX_CLK					145

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				146

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				147

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				148

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				149

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				150

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				151

#define GCC_USB30_PRIM_MASTER_CLK				152

#define GCC_USB30_PRIM_MASTER_CLK_SRC				153

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				154

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			155

#define GCC_USB30_PRIM_SLEEP_CLK				156

#define GCC_USB30_SEC_MASTER_CLK				157

#define GCC_USB30_SEC_MASTER_CLK_SRC				158

#define GCC_USB30_SEC_MOCK_UTMI_CLK				159

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				160

#define GCC_USB30_SEC_SLEEP_CLK					161

#define GCC_USB3_PRIM_CLKREF_CLK				162

#define GCC_USB3_PRIM_PHY_AUX_CLK				163

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				164

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				165

#define GCC_USB3_PRIM_PHY_PIPE_CLK				166

#define GCC_USB3_SEC_CLKREF_CLK					167

#define GCC_USB3_SEC_PHY_AUX_CLK				168

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				169

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				170

#define GCC_USB3_SEC_PHY_PIPE_CLK				171

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				172

#define GCC_VIDEO_AHB_CLK					173

#define GCC_VIDEO_AXI_CLK					174

#define GCC_VIDEO_XO_CLK					175

#define GPLL0							176

#define GPLL0_OUT_EVEN						177

#define GPLL0_OUT_MAIN						178

#define GPLL1							179

#define GPLL1_OUT_MAIN						180



/* RPMh controlled clocks */

#define RPMH_CXO_CLK						0